Instruction sets and their implementation

[TuxDave]

And option #3 - if AMD wanted to make their customer's experience with x87 applications be comparable to what Intel's customers experience then AMD could prioritize it and make it so.

When the road is bumpy and Ford makes it a smooth ride by equipping their cars with superior, and more expensive, shock absorbers it would be kinda backwards for Dodge car owners to expect the city to make the roads smoother just for them so they can experience what Ford owners experience already.

Dodge should equip their cars with shock absorbers too, if they wanted their customers to have a smoother ride that is. But if they don't, well then Dodge's customers are kinda getting exactly what they paid for and deserve at that point, right?

I could agree with that. From what I can tell, it's just "risk management". I don't kill performance on x87 because I hate it. I only cripple it a little if it gets in the way of something else I need to get done. So maybe you can say someone at AMD has done a far better job at chucking the whole thing in the trash than I have.

 

[Cerb]

Are OS's and programs built in much the same way then? Would Win7 benefit from those ISA's(I'm guessing any and all software could) and could they be implemented through an update?

Yes and no. For the ISA stuff we're talking about, maybe, but not in the sense they would improve their own performance (SMP feature support being a notable exception). It may need an update to allow applications to use the new features, since they can have CPU state side-effects (old applications could be affected by leftover register changes from new applications), and backwards-compatibility is sometimes built in (special ways to do emulation, or fall back to old-style routines).

The most important new features for the OS tend to be features they have to add explicit support for, such as power management (APM, ACPI), firmware (BIOS, UEIF), APICs (LAPIC, IOAPIC), and the like. These typically require new interfaces to be written (sometimes direct to hardware, sometimes to talk to 3rd-party drivers), wrappers to old interfaces, and often new user interfaces, too. So, you generally have to wait a version or two.

 

[FalseChristian]

What the hell are you guys saying. I have an I.Q. of 127 and I don't understand a word you guys are writing. Please explain these instruction sets in layman's terms. Thank you.

 

[guskline]

What the hell are you guys saying. I have an I.Q. of 127 and I don't understand a word you guys are writing. Please explain these instruction sets in layman's terms. Thank you.

I couldn't have said it better!:biggrin:

 

[Sleepingforest]

From what I understand: An ISA is the "instruction set architecture." It's basically how the software (OS, programs, etc) communicate with the actual hardware.

Programs aren't written in a way a computer intrinisically understands--a computer only really understands 1s and 0s at the end of the day. So programmers put what they want the computer to say into code using "high level" languages, like Java, Python, and so on. A "compiler" turns this into something that the computer (the actual CPU/GPU) can understand.

Better ISAs are desirable in that they communicate with the CPU more effectively/efficiently. But people who make compilers have to optimize for new ones (create the translation methodology) before the wider audience of programmers and developers can take advantage of it.

 

[Torn Mind]

What the hell are you guys saying. I have an I.Q. of 127 and I don't understand a word you guys are writing. Please explain these instruction sets in layman's terms. Thank you.

Goes to show that intelligence itself does not guarantee instant comprehension, although the speed at which you reach a state of comprehension can be much faster than those of lower intelligence.

Anyway, I too have not gotten a "low-level" grasp of ISAs, but I do know at a high level, they help apps that utilize them perform faster.

 

[NTMBK]

What the hell are you guys saying. I have an I.Q. of 127 and I don't understand a word you guys are writing. Please explain these instruction sets in layman's terms. Thank you.

In all honesty, one of the best ways to get a handle on these things is just to drill down into the documentation. The MSDN stuff is a good place to start: http://msdn.microsoft.com/en-us/library/26td21ds(v=vs.100).aspx Just go straight into the sections about MMX and SSE1-4.

 

[VirtualLarry]

I just wanted to add, that the OS can actually emulate opcodes (instructions in the ISA) that aren't implemented by the processor, to some extent. If the processor throws an invalid opcode exception, then the CPU faults, and the kernel can then look at the user-mode thread's instruction stream, and emulate it in software.

This is how the 386 CPU could run x87 floating-point code in Windows apps, on a CPU without a math co-processor. Yes, it was much slower than if you had a real FPU (like on a 486, or with a co-proc), but at least it ran.

There's no reason that MS couldn't implement AVX2 in software too, to speed adoption of that opcode for Intel, and provide support for those opcodes on lower-end Intel CPUs that have had their AVX2 'nads chopped off at the factory.

 

[ShintaiDK]

It doesnt work that way. You simply had multiple execution paths like today.

It makes no sense to do "slower AVX2" either. A program supports multiple options. AVX, SSE etc. And then pick the path that the CPU supports. Its not like a AVX2 supporting program today wont run on anything less than a AVX2 supporting CPU. Already plenty of AVX2 applications out there, but no CPUs yet.

 

[VirtualLarry]

It doesnt work that way.

Actually, it does. Read Intel's docs on exceptions.

 

[Idontcare]

From what I understand: An ISA is the "instruction set architecture." It's basically how the software (OS, programs, etc) communicate with the actual hardware.

Programs aren't written in a way a computer intrinisically understands--a computer only really understands 1s and 0s at the end of the day. So programmers put what they want the computer to say into code using "high level" languages, like Java, Python, and so on. A "compiler" turns this into something that the computer (the actual CPU/GPU) can understand.

Better ISAs are desirable in that they communicate with the CPU more effectively/efficiently. But people who make compilers have to optimize for new ones (create the translation methodology) before the wider audience of programmers and developers can take advantage of it.

The ISA is just the entire list of instructions that a CPU can be asked to compute.

Asking a CPU to compute A*B = C (multiplication) is just one instruction. Addition would be another. Division would be yet another instruction.

All those instructions in total equal the "instruction set" which the CPU can be expected to support.

The ISA has been expanded with every major new microarchitecture release.

Today's processors support nearly 2000 instructions in their ISA. Those instructions are all there to enable faster (or more energy efficient) calculations of everything under the sun from addition to square roots to the value of Sin(37.856°), etc.

 

[ThePeasant]

Already plenty of AVX2 applications out there, but no CPUs yet.

Could you quantify "plenty"?

 

[TuxDave]

Could you quantify "plenty"?

Whatever these guys are running?

http://www.datacenterknowledge.com/archives/2012/12/07/stampede/

 

[Exophase]

Whatever these guys are running?

http://www.datacenterknowledge.com/archives/2012/12/07/stampede/

Somehow I don't think so, since Xeon Phi runs LRBNI and not AVX2 (or AVX or any level of SSE for that matter) as its vector instruction set.

 

[TuxDave]

Somehow I don't think so, since Xeon Phi runs LRBNI and not AVX2 (or AVX or any level of SSE for that matter) as its vector instruction set.

I think that's right. My bad.

 

[Namira Fang]

Thank you all for the lesson. Lots of good info here and I have a much better grasp on ISA's.

 

[Borkil]

As others have explained an instruction is a command that a cpu can understand and perform an operation. An instruction set is just the set of all commands/instructions. Thinki of an instruction set as the vocabulary of a cpu and an instruction is a word in the vocabulary. How they are built into the computer depends on the cpu. One way is there is a controller block that looks at the instruction and parses the data into control signals. These control signals determine where the data is sent and what is done with the data. Here is a diagram for a simple single cycle MIPS cpu.

The big oval in the middle is the control block. It tells the other blocks (ALU, Register file, muxes, Memory/dcache) what to do with the data. In order to add new instructions you need to change the control block to be able to recognize a new instruction and to appropriately set the correct control flags needed. Along with actually making sure the rest of the blocks can do their correct behavior as well. For the internals of the control block it is simple combinational logic, just an and/or grid.

The ands at the top of the grid represent some of the opcodes/instructions that can be performed. The ors on the right represent the control signals. For example the "RegWrite" control signal (which tells the cpu to save the result to a register) will go high when an rtype, ori, or an lw instruction is being decoded. Again this is just a simple MIPS example. Today's x86 are more complicated and will look a little different. But this is a general way to implement an ISA

 

[Namira Fang]

Borkil, many many thanks. I'm not gonna pretend to fully understand those diagrams but they and your explanation of them helps tremendously. I'm not an engineer so I'm never gonna have that degree of knowledge but as a hobbyist it's always nice to know more. It's always fascinated me how tech works.

 

[Idontcare]

Borkil, many many thanks. I'm not gonna pretend to fully understand those diagrams but they and your explanation of them helps tremendously. I'm not an engineer so I'm never gonna have that degree of knowledge but as a hobbyist it's always nice to know more. It's always fascinated me how tech works.

Not that it makes for easy reading, but this might help answer some questions. (or it might put you to sleep! )

 

[Namira Fang]

Well, I am an insomniac. So win win right?

 

[Idontcare]

Well, I am an insomniac. So win win right?

LOL, that made me bust a gut