Hans de Vries predicted a 6.2 track cell layout when the IEDM 2017 paper was presented. Kudos to Hans for his fantastic observation and analysis. For those who do not have a semiwiki login I will post it here with full credit to Hans de Vries.
Just a tidbit: The "cell-size" MMP x CPP of
Intel's process is actually 40 x 54 = 2160 nm2 (using M0) or even 44 x 54 = 2376 nm2 (using M2)
This is because the M1 lines run in parallel with the gates, with a pitch ratio of 36:54 = 2:3. You can see it in this photo over at Dick's article where M1 is just visible at the top of the image.
In Intel's 14nm they used M2P x CPP = 52 x 70 = 3640 nm2 and M2 scaled from 52nm to 44nm.
This makes the Track number 7.65 (=272:36) a bit odd. A better number, using M2 as in your example image the track count would be 272:44 = 6.2 tracks
The odd thing is the track size 272:36 = 7.55. The only 36nm (M1) lines run parallel with the gates...
Maybe they relaxed some layers from an original 36 nm to 44 nm and went from a 7.5 track design to a 6 track design to keep the Logic cell size equal...
That would look like this I presume: