https://semiengineering.com/manufacturing-bits-dec-5/
"Intel’s 10nm technology represents the company’s third-generation finFET technology. The technology shows the characteristics of a steep subthreshold slope device (~70 mV/dec).
The process makes use of 193nm immersion lithography and self-aligned quadruple patterning (SAQP). As previously stated, the process includes self-aligned contact over active gate scheme. The technology features 12 metal layers with ultra-low-k dielectrics. In a first for the industry, the technology will also incorporate cobalt materials at three local interconnect layers.
Intel and other chipmakers are following the same transistor path at 10nm and 7nm–they are extending the finFET and making the fins taller and thinner, which in turn boosts the drive current. At 7nm, Intel’s transistors feature rectangular fins with 7nm fin width and 46nm fin height, according to a paper from Intel.
At 10nm, Intel’s fin pitch is 34nm and the fin height is 53nm.
Using SAQP at the metal-0 and metal-1 layers, Intel achieved fin pitches down to 34nm and metal pitches of 36nm. “Scaling of density critical interconnect layers is up to 0.51x versus the traditional 0.7x,” according to Intel’s paper.
The interconnect stack has 12 layers. “Cobalt is introduced at the lowest two interconnect layers providing a 5-10x improvement in electromigration and a 2x reduction in via resistance,” according to the paper. “A cobalt cladding layer is utilized at Metal 2 – Metal 5 to improve electromigration. Low-k CDO dielectrics are used on 11 layers.”
Meanwhile, GlobalFoundries will present more details about its 7nm finFET process. Compared to 14nm, the 7nm process has a performance increase of >40% at fixed power, or power reduction of >55% at fixed frequencies, according to the company.
The technology makes use of SAQP for fin formation and SADP for the wiring schemes. Initially, GlobalFoundries won’t use extreme ultraviolet (EUV) lithography at 7nm. But the process is designed to leverage EUV when the technology is ready.
GlobalFoundries’ finFETs have a fin pitch of 30nm, a contacted gate pitch of 56nm, and a metal pitch of 40nm.
Multiple copper level stacks are offered to enable a range of SoC applications, according to GlobalFoundries. One example of a general purpose SoC is a 13-level stack. “Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL),” according to GlobalFoundries.
Intel 10nm vs GF 7nm (7SoC)
Intel 10nm
CPP = 54nm
MMP = 36nm
Fin Pitch = 34nm
Fin Height = 46nm
12 Metal layers
Tracks = 7.56
6transistor HD SRAM cell = 0.0312 um
GF 7SoC
CPP = 56nm
MMP = 40nm
Fin Pitch = 30nm
Fin Height = Not revealed yet
13 Metal layers
Tracks = 6
6transistor HD SRAM cell = 0.0269 um
https://www.semiwiki.com/forum/cont...alfoundries-discloses-7nm-process-detail.html