- Dec 25, 2013
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First, from the Investor Meeting in November:
Intel is quietly delaying its process ramp at the 10nm node, according to multiple sources.
This is contrary to what Makr Bohr suggested at ISSCC and IEDM in the past months:
Happy 50th anniversary, Moore's Law :thumbsdown: (well, it's still 6 days).
The gross margin impact was supposed to be -1.0 points in Q4'14; it turned out to be -0.5 points. For Q1'15, Stacy estimated a -1.5 points drop from increased factory spending. This, apparently, will not be the case:“But you are seeing in the fourth quarter, you’re seeing the front edge of the startup cost associated with the 10-nanometer and that’s kind of right in line with the historical timing of what you’d expect.” Stacy Smith, CFO Intel, IM’14
Intel is quietly delaying its process ramp at the 10nm node, according to multiple sources.
In an e-mail, a spokesman for Intel said: “We have not disclosed a schedule for our 10nm process and we won’t engage in speculation about it.”
In March, though, Intel was supposed to make fab tool buys for high-volume manufacturing at 10nm, sources said. But now, those purchases won’t happen until December of this year, according to sources.
The company is setting up a small pilot line for 10nm production in Oregon, but the 10nm production fab will actually be located in Israel. In 2008, Intel opened its second fab in Kiryat Gat, Israel. That plant, Fab 28, is a high-volume manufacturing fab, which runs 300mm wafers on a 45nm process technology. That fab is being upgraded and expected to run 10nm technology.
10nm volume production may occur in 2016, which is later than expected. The reported move to push out its 10nm node follows delays at 14nm. Intel moved into production at 14nm late last year, which was six or so months later than expected. Intel blamed the delay on yield issues.
This is contrary to what Makr Bohr suggested at ISSCC and IEDM in the past months:
It was explained that while 10nm will have more masking steps than 14nm, and the delays that bogged down 14nm coming late to market will not be present at 10nm – or at least reduced. We were told that Intel has learned that the increase in development complexity of 14nm required more internal testing stages and masking implementations was a major reason for the delay, as well as requiring sufficient yields to go ahead with the launch. As a result, Intel is improving the efficiency testing at each stage and expediting the transfer of wafers with their testing protocols in order to avoid delays. Intel tells us that that their 10nm pilot lines are operating 50% faster than 14nm was as a result of these adjustments.
“We don’t expect we’ll have similar problems at 10 nm, because we’ve learned and we’re trying harder,” he said.
Happy 50th anniversary, Moore's Law :thumbsdown: (well, it's still 6 days).