Intel 10nm delayed by 9 months? (Semiengineering)

[witeken]

First, from the Investor Meeting in November:

“But you are seeing in the fourth quarter, you’re seeing the front edge of the startup cost associated with the 10-nanometer and that’s kind of right in line with the historical timing of what you’d expect.” Stacy Smith, CFO Intel, IM’14

The gross margin impact was supposed to be -1.0 points in Q4'14; it turned out to be -0.5 points. For Q1'15, Stacy estimated a -1.5 points drop from increased factory spending. This, apparently, will not be the case:

Intel is quietly delaying its process ramp at the 10nm node, according to multiple sources.

In an e-mail, a spokesman for Intel said: “We have not disclosed a schedule for our 10nm process and we won’t engage in speculation about it.”

In March, though, Intel was supposed to make fab tool buys for high-volume manufacturing at 10nm, sources said. But now, those purchases won’t happen until December of this year, according to sources.

The company is setting up a small pilot line for 10nm production in Oregon, but the 10nm production fab will actually be located in Israel. In 2008, Intel opened its second fab in Kiryat Gat, Israel. That plant, Fab 28, is a high-volume manufacturing fab, which runs 300mm wafers on a 45nm process technology. That fab is being upgraded and expected to run 10nm technology.

10nm volume production may occur in 2016, which is later than expected. The reported move to push out its 10nm node follows delays at 14nm. Intel moved into production at 14nm late last year, which was six or so months later than expected. Intel blamed the delay on yield issues.

This is contrary to what Makr Bohr suggested at ISSCC and IEDM in the past months:

It was explained that while 10nm will have more masking steps than 14nm, and the delays that bogged down 14nm coming late to market will not be present at 10nm – or at least reduced. We were told that Intel has learned that the increase in development complexity of 14nm required more internal testing stages and masking implementations was a major reason for the delay, as well as requiring sufficient yields to go ahead with the launch. As a result, Intel is improving the efficiency testing at each stage and expediting the transfer of wafers with their testing protocols in order to avoid delays. Intel tells us that that their 10nm pilot lines are operating 50% faster than 14nm was as a result of these adjustments.

“We don’t expect we’ll have similar problems at 10 nm, because we’ve learned and we’re trying harder,” he said.

Happy 50th anniversary, Moore's Law :thumbsdown: (well, it's still 6 days).

 

[Enigmoid]

Not surprising. 10nm on the heels of 14nm was overly optimistic.

 

[NTMBK]

How remarkable that nobody saw this coming!

It sucks, but its hardly surprising.

 

[Arachnotronic]

Not surprising. 10nm on the heels of 14nm was overly optimistic.

TSMC says that its 10nm will go into production by EOY 2016, when 16FF+ will go into production in mid-2015...

 

[erunion]

I guess it depends on what one means by delayed. The article says delayed into 2016. If Cannonlake is available for holiday '16(about 15 months after skylake), that'd be best case scenario. I wouldn't call that a delay.

 

[jpiniero]

I guess it depends on what one means by delayed. The article says delayed into 2016. If Cannonlake is available for holiday '16(about 15 months after skylake), that'd be best case scenario. I wouldn't call that a delay.

Cannonlake was never really going to happen in 2016, more like early 2017. I'd be surprised if it was delayed 9 months from then... maybe something more like mid 2017.

We'll probably see Skylake Refresh for all parts now.

 

[Idontcare]

TSMC says that its 10nm will go into production by EOY 2016, when 16FF+ will go into production in mid-2015...

16FF+ is basically taking 20nm and finally releasing it with the transistors it was supposed to have had all along.

10nm is essentially TSMC's 14nm.

From a technology timeline standpoint, you need to compare 20nm versus 10nm release timelines to get something which is apples-to-apples comparable to Intel's 22nm to 14nm, or 14nm to 10nm, release timeline.

 

[erunion]

Cannonlake was never really going to happen in 2016, more like early 2017. I'd be surprised if it was delayed 9 months from then... maybe something more like mid 2017.

We'll probably see Skylake Refresh for all parts now.

I agree that early 2017 is a reasonable time frame for cannonlake. But nothing in the article suggests it will be delayed later than, it mentions ramping in 2016 instead of 2015; still consistent with a q1-17 or even q4-16 launch.

While that may be considered delayed versus a 2 year old roadmap, I'd consider that launch window appropriate following a August launch of skylake.

 

[jhu]

9 whole months? That's an entiree pregnancy!

 

[jpiniero]

I agree that early 2017 is a reasonable time frame for cannonlake. But nothing in the article suggests it will be delayed later than, it mentions ramping in 2016 instead of 2015; still consistent with a q1-17 or even q4-16 launch.

That seems way too aggressive. Doesn't it take 3 months to turn around a chip and then another month or two to build volume? I was thinking more like they begin final production in Dec 2016 and launch in May.... and that's if everything goes right.

 

[erunion]

That seems way too aggressive. Doesn't it take 3 months to turn around a chip and then another month or two to build volume? I was thinking more like they begin final production in Dec 2016 and launch in May.... and that's if everything goes right.

But if it was delayed by 9 months, from sometime in 2015 to 2016, the absolute latest it could begin would be September 2016. ( 9 months after December '15)

 

[Hulk]

After curve fitting the previous 4 tick release dates I'm going to predict 10nm will be available for purchase on December 8, 2016.

 

[Arachnotronic]

16FF+ is basically taking 20nm and finally releasing it with the transistors it was supposed to have had all along.

10nm is essentially TSMC's 14nm.

From a technology timeline standpoint, you need to compare 20nm versus 10nm release timelines to get something which is apples-to-apples comparable to Intel's 22nm to 14nm, or 14nm to 10nm, release timeline.

Fair enough

 

[Idontcare]

Fair enough

The only reason we, as outsiders, are justified in expecting TSMC's 10nm to be any different than past nodes is the fact that TSMC went and doubled their R&D team pipeline just to ensure 10nm hit its delivery date.

Were TSMC approaching 10nm the same as they approached 40, 28, 20, and 16 then I'd be inclined to expect more of the same roadmap slippage from them. But something motivated TSMC to make a marked change in their approach to 10nm development.

They want to dominate 10nm like they did 28nm. This is huge to them.

And of course there is other stuff which we can learn about through unofficial channels, but even in the absence of that other stuff we ought to feel compelled to give TSMC the benefit of the doubt on this one when it comes to 10nm expectations. I do at least, for what its worth.

 

[Exophase]

If we're giving TSMC the benefit of the doubt, they've also been saying that 10nm will have a higher than usual density improvement (where "the usual" doesn't mean 20nm->16nm but 28nm->20nm). But then again, Intel did the same thing for 14nm and they say they will again for 10nm, so maybe TSMC 10nm will still be like Intel 14nm in density.

 

[carop]

If we're giving TSMC the benefit of the doubt, they've also been saying that 10nm will have a higher than usual density improvement (where "the usual" doesn't mean 20nm->16nm but 28nm->20nm). But then again, Intel did the same thing for 14nm and they say they will again for 10nm, so maybe TSMC 10nm will still be like Intel 14nm in density.

How do you benchmark a process?

Thanks.

 

[Idontcare]

How do you benchmark a process?

Thanks.

Step 1: Attend IEDM

Step 2: Invite select individuals out for dinner and drinks

Step 3: Convince select individuals to continue drinking (and chatting) well into the evening

Step 4: Learn all you need to know about the parametric and physical details of the node

Step 5: Tell no one what you learned, they'll just respond with "pics or it didn't happen" if you bother trying :\

 

[witeken]

How do you benchmark a process?

Thanks.

You don't. You let the company itself do that (but not on Powerpoint slides) and you take their claims for granted: http://www.intel.com/content/dam/ww...foundry/intel-14nm-iedm-2014-presentation.pdf.

If you know the transistor count and die sizes of two dies (from the same product family) then you can calculate the density improvement yourself.

 

[carop]

Step 1: Attend IEDM

Step 2: Invite select individuals out for dinner and drinks

Step 3: Convince select individuals to continue drinking (and chatting) well into the evening

Step 4: Learn all you need to know about the parametric and physical details of the node

Step 5: Tell no one what you learned, they'll just respond with "pics or it didn't happen" if you bother trying :\

Thanks, but I am trying to understand the basis of "maybe TSMC 10nm will still be like Intel 14nm in density."

How will "TSMC 10nm will still be like Intel 14nm in densiy?"

Thanks again.

 

[ShintaiDK]

The nm is essentially just a random marketing number.

 

[MisterMac]

@IDC:

Would you say given what we're potentially seeing - that Intel has slept too much on it dominant node position and may now start loosing some of it's advantage?

It seems despite the turncoats in taiwan - both TSMC & Samsung are (while not 100% comparable in parametric\physical sizes) maybe catching up to confident chipzilla?

 

[witeken]

Would you say given what we're potentially seeing - that Intel has slept too much on it dominant node position?

No.
It does not in any way follow that a delay because of yield issues means Intel is sleeping. It's simply hard.

Advancing Moore's Law is always a good thing. If Intel wants to sleep, they can stop adding transistors while the lower cost per transistor from smaller nodes will improve margins. But that is not how the technology industry works.

 

[Arachnotronic]

If we're giving TSMC the benefit of the doubt, they've also been saying that 10nm will have a higher than usual density improvement (where "the usual" doesn't mean 20nm->16nm but 28nm->20nm). But then again, Intel did the same thing for 14nm and they say they will again for 10nm, so maybe TSMC 10nm will still be like Intel 14nm in density.

Here's a way to sanity check that...

TSMC 16FF GP x MxP = (90)(64) = 5760.

Shrink 5760 by 2.1 to get ~2742

Intel 14nm GP x MxP = (70)(52) = 3640

Shrink 3640 by 2.1 (slightly better than 2x) to get ~1733

2742 is closer to 3640 than it is to 1733, but the TSMC 10nm node should be denser than Intel 14nm.

If I had to guess, I'd say TSMC 10nm features a gate pitch of 64nm and a minimum metal pitch of 44nm...

 

[simboss]

Here's a way to sanity check that...

TSMC 16FF GP x MxP = (90)(64) = 5760.

Shrink 5760 by 2.1 to get ~2742

Intel 14nm GP x MxP = (70)(52) = 3640

Shrink 3640 by 2.1 (slightly better than 2x) to get ~1733

2742 is closer to 3640 than it is to 1733, but the TSMC 10nm node should be denser than Intel 14nm.

If I had to guess, I'd say TSMC 10nm features a gate pitch of 64nm and a minimum metal pitch of 44nm...

Impressive how R&D budgets of billions of $ and thousands of engineers can be reduced to 3 simple numbers

 

[mikk]

I don't see anything new here. Someone from Intel told some time ago that first 10nm products are expected to launch early 2017. That means 10nm production start not before H2 2016.

http://gulfnews.com/business/sectors/technology/intel-to-launch-10nm-chips-in-early-2017-1.1443856