Quick tidbits from the call:
- Lunar Lake fabrication was "almost entirely outsourced".
Intel explained the original plan for Lunar Lake. It was tailored to cover only a small segment / niche of very low power thin and light. A new segment for Intel, something equivalent to Mac Air.
The intention was to establish Intel in this segment at whatever the cost would be and later, to capitalize with Panther Lake.
The problem is that MTL sucks, and now Intel needs Plan 2 for MTL sucking, which is Lunar Lake in greater volume.
But since Lunar Lake was to be only demonstration project, not a volume product, regardless of cost, now Intel is stuck trying to ship very expensive chip to higher volume (assuming TSMC will offer Intel more capacity).
- On-package memory also will hurt Lunar Lake margins.
It will hurt margin
percentage, not margin
dollars.
Intel management, and certain financial analyst had a fetish of margin percentage, which lead to Intel destroying / divesting itself from number of market segments, rather than continue to sell lower margin
percentage, while still earning margin
dollars.
So, this is not really a problem for Lunar Lake, other than analysts beating Intel over the head with this.
- Biggest CCG margin killer: Meteor Lake was designed to ramp on Oregon fabs. But Intel made a late-breaking switch to Ireland fabs: problematically, Ireland fabs have "a much higher wafer cost" and costs will stay higher in the next quarter.
This was not fully explained why Intel moved the production, but I think the hint was that Ireland fab can produce higher volume, while Oregon fab is more research oriented.
We can speculate why, what is pressing Intel to manufacture more MTLs than originally planned, even when such a change of plan is very costly.
I think the reason may be Raptor Lake instability. Why else would Intel want to maximize production of MTL, even though MTL is not the most successful or most profitable chip. It's because MTL is not RPL.