All told, Intel is shooting for a better than 5% IPC improvement over Haswell. This is similar to Ivy Bridge (4%-6%), though at this stage in the game Intel is not talking about expected clockspeeds or the resulting overall performance improvement. Intel has made it clear that they dont regress on clockspeeds, but beyond that well have to wait for further product details later this year to see how clockspeeds will compare.
To accomplish this IPC increase Intel will be relying on a number of architectural tweaks in Broadwell. Chief among these are bigger schedulers and buffers in order to better feed the CPU cores themselves. Broadwells out-of-order scheduling window for example is being increased to allow for more instructions to be reordered, thereby improving IPC. Meanwhile the L2 translation lookaside buffer (TLB) is being increased from 1K to 1.5K entries to reduce address translation misses.
In Haswell-Y Intel used a GT2 configuration, which was composed of a single slice that in turn contained 2 sub-slices. In Intels GPU architecture the sub-slice is the smallest functional building block of the GPU, containing the EUs (shaders) along with caches and texture/data/media samplers. Each EU in turn was composed of 2 4-wide vector SIMDs, with 10 EUs per sub-slice.
For Broadwell Intel is not changing the fundamental GPU architecture, but they are rebalancing the number of EUs per sub-slice and increasing the number of sub-slices overall. As compared to Haswell, Broadwells sub-slices will contain 8 EUs per sub-slice, with a complete slice now containing 3 sub-slices. Taken altogether this means that whereas Haswell-Y was a 2x10EU GPU, Broadwell-Y will be a 3x8EU GPU.
The ramifications of this is that not only is the total number of EUs increased by 20% from 20 to 24, but Intel has greatly increased the ratio of L1 cache and samplers relative to EUs. There is now 25% more sampling throughput per EU, with a total increase in sampler throughput (at identical clockspeeds) of 50%. By PC GPU standards increases in the ratio of samplers to EUs is very rare, with most designs decreasing that ratio over the years. The fact that Intel is increasing this ratio is a strong sign that Haswells balance may have been suboptimal for modern workloads, lacking enough sampler throughput to keep up with its shaders.
What Intel is doing however is reiterating the benefits of their 14nm process in this case, noting that because 14nm significantly reduces GPU power consumption it will allow for more thermal headroom, which should further improve both burst and sustained GPU performance in TDP-limited scenarios relative to Haswell.
But even thats still not enough, and for Core M Intel went so far as to give Broadwell-Y its own die and design a low-power optimized version of their 14nm process just for it. This variant is designed to further reduce power consumption by optimizing the resulting transistors for lower power, lower voltage, lower clockspeed operation. By doing this Intel was able to further reduce power consumption in all of the major areas over what would be a traditional 14nm Intel process.
In the resulting 14nm Broadwell-Y process, voltage, capacitance, and leakage were all improved over the traditional 14nm process. Capacitance was reduced by 15%, minimum operating voltages by 10%, and leakage was improved to the point that it reduced SoC power consumption by 10%. The combination of all of these factors serves to significantly lower power consumption over what Intels traditional 14nm process would provide.
Working in concert with Broadwell-Ys 14nm process, Intel has made a number of other changes to further reduce power consumption. Some of these are reflected in Broadwells overall design and others are unique to Broadwell-Y, such as using a lower TjMax for Broadwell-Y. By reducing the maximum operating temperature of the chip Intel has been able to realize further power savings by further reducing voltage and decreasing the maximum amount of temperature-dependent leakage the SoC will experience.
But even thats still not enough, and for Core M Intel went so far as to give Broadwell-Y its own die and design a low-power optimized version of their 14nm process just for it.
Looking forward to seeing this in devices. My Haswell-Y 2-in-1 is a pretty sweet device, but eliminating the fans and dropping the thickness would be the real cherry on top.
Don't get me wrong, I'm happy for any Broadwell information, but we knew about 30% power reduction many months ago and we also know from experience 5% IPC improvement is about what to expect. There are some other good tidbits but I'm personally looking for some sku specs.
Man, they really changed the layout on the cores.
This 'Broadwell + 14nm = Core M' IDM cooperation is really working out great. Unfortunately Core M is only aiming at $600+.
The information about Gen8 confuses me. It was said to be a giant improvement, but Anand says there are no architectural improvement (in contradiction with the slide). Is it me or does it seem like they could have already done this (sub-)slice balancing in Gen7(.5)? So what performance and power improvements will the raw Gen8 architecture bring? I remember from the Iris Pro review that the amount of FPS/GFLOPS was weak compared to the competition, so if this balancing brings them on par with the competition, I guess we'll see an additional 20% or so improvement with the 20% EU increase.
Now we know more specific details and we know how they managed to do all those things, which I think is more interesting than plain benchmarks.
BTW, (some of) the SKUs' specs already leaked. 4.5W TDP, cTDP of 4W, 0.8-1.1GHz base speed to over 2GHz turbo.
http://download.intel.com/newsroom/...h_Generation_Intel_Core_Dual_Core_Hero_HR.jpgDid they? Do we have dualcore Haswell die images?
Have you actually listened to the webcast? Here's the summary of what they did in the previous generations and the webcast was about how they'll improve it with Broadwell:Not trying to be "cheeky" but they did it the same way they always do it. Process shrink and some minor architectural improvements.
Lets see how that will affect pricing.
Man, they really changed the layout on the cores.
For Broadwell Intel is not changing the fundamental GPU architecture, but they are rebalancing the number of EUs per sub-slice and increasing the number of sub-slices overall. As compared to Haswell, Broadwells sub-slices will contain 8 EUs per sub-slice, with a complete slice now containing 3 sub-slices. Taken altogether this means that whereas Haswell-Y was a 2x10EU GPU, Broadwell-Y will be a 3x8EU GPU
So it's 3x8 (24 EUs) for Broadwell-Y - presumably GT2 and 2x8 (16 EUs) for Cherry Trail / Braswell, what about Broadwell GT1? Not sure if such SKU exists, but still...
I just started reading AnandTech's coverage and I see that, surprisingly, it isn't Anand, CPU editor, who wrote the 2 articles but Ryan smith, GPU editor. It seems Anand is busy reviewing smartwatches.