Intel Broadwell Thread

[III-V]

I hear this a lot, but I see just the opposite in benchmarks and in real world experience. I'm talking about 28nm vs 22nm SoC.

What do you mean by "real world experience?" The human benchmark is a terrible one.

Are you basing this on the Apple A7 vs. Bay Trail? Because there, the gap is even larger. Samsung uses gate-first on their 28nm process, which is inherently inferior to gate-last as far as performance goes.

TSMC 20nm is a more advanced, more dense process and it's available now. I really hope Intel delivers with 14nm. I am planning on buying Broadwell-U immediately, just as I bought Sandy bridge and Haswell on release.

Denser, yes. More advanced, no. It's a planar process, for one. TSMC trails Intel by 1-2 nodes in performance. Right now, they're trailing by one. In just about a week, it'll be back to two again.

I only skipped ivy bridge, and I think we can all agree the 3770K was disappointing

In what sense?

 

[NostaSeronx]

Samsung uses gate-first on their 28nm process, which is inherently inferior to gate-last as far as performance goes.

Actually, Gate Last is the inherently inferior gate stack model.

MIPS is not the only Gate First way to do a gate stack.
RMG is not the only Gate Last way to do a gate stack.

Just to drop a bomb III-V, GaAs has superior performance with Gate-First than with Gate-Last.

Denser, yes. More advanced, no. It's a planar process, for one. TSMC trails Intel by 1-2 nodes in performance. Right now, they're trailing by one. In just about a week, it'll be back to two again.

Planar is the more advanced process. Especially, when III-V materials start being used.

Planar is flexible and cheap.
Planar is low leakage and high performance.
Planar scales down to monolayers.

FinFETs are just a small short-term fix, to a non-problem. It is wasted effort and it doesn't even do what it is promised to do.

------
Also, for those interested in the correct path note that there are three FDSOI nodes;
FDSOI
SG-ETSOI
DG-ETSOI

UTBB FDSOI is the same as DG-ETSOI. The title for fastest transistors coming in 2015. Goes to 14-nm DG-ETSOI by STMicrolectronics. Everyone ignored the research papers and the prototypes. I hope those in the foundry business prep for the SOI wave. You are in for a massive treat. When the first 14-nm FDSOI application processor hits the market(and presentations before that).

 

[III-V]

It is absolutely baffling that you are attempting to disprove what I've stated with technologies that don't apply.

Samsung and Globalfoundries do use metal-inserted poly si on 28nm. It is useless to talk about theoretical what-ifs in scope of this discussion.

 

[NostaSeronx]

It is absolutely baffling that you are attempting to disprove what I've stated with technologies that don't apply.

I was pointing to the continued benefits of Gate First.

Samsung and Globalfoundries do use metal-inserted poly si on 28nm.

I never said otherwise. MIPS, while have shortcomings are easily designed around. People have brains in which they solve problems with. RMG isn't the only Gate Last solution, and there is several hybrid solutions. My findings point to Gate First(dielectric-last and metalgate-first) having the overall best characteristics. All the way down to <1-nm graphene planar monolayer CMOS.

It is useless to talk about theoretical what-ifs in scope of this discussion.

Just dropping the bomb that initial what if papers about ETSOI. That they were wrong and FinFETs aren't the fastest approach nor the Moore's Law approach.

14-nm FinFETs while nice looking on paper won't be the main focus of 2015. Celebratory clap.. nice job Intel!

Now which architecture on 14-nm Intel FinFETs will be competing with 14-nm FDSOI AArch64 architectures. I'm leaving this one open for custom AArch64, you never know when you'll get blind-sided.

 

[witeken]

I was really hoping to get he broadwell MacBook Air but it's looking like that actually might be a downgrade unless I'm misunderstanding broadwell turbo.

The i7 in the MacBook Air is a 4650U

http://ark.intel.com/m/products/75114/Intel-Core-i7-4650U-Processor-4M-Cache-up-to-3_30-GHz

How is Core M with the same amount of cache, much lower base and much lower turbo going to keep up with Haswell?

I really hope Intel has kept a secret SKU for apple that will help core M compete with haswell (currently clocked 600MHz higher than 5Y70). I want Broadwell to be good and I like haswell too, but I think apple will have something special for the MacBook line this year.

Broadwell is presumably going to keep up with 11.5W Haswell-Y. But compared to fanless ARM, Broadwell will blow its competition away.

 

[III-V]

I was pointing to the continued benefits of Gate First.I never said otherwise. MIPS, while have shortcomings are easily designed around. People have brains in which they solve problems with. RMG isn't the only Gate Last solution, and there is several hybrid solutions. My findings point to Gate First(dielectric-last and metalgate-first) having the overall best characteristics. All the way down to <1-nm graphene planar monolayer CMOS.Just dropping the bomb that initial what if papers about ETSOI. That they were wrong and FinFETs aren't the fastest approach nor the Moore's Law approach.

14-nm FinFETs while nice looking on paper won't be the main focus of 2015. Celebratory clap.. nice job Intel!

Now which architecture on 14-nm Intel FinFETs will be competing with 14-nm FDSOI AArch64 architectures. I'm leaving this one open for custom AArch64, you never know when you'll get blind-sided.

I'm happy to hear that SOI is finally shaping up to be something less than a disaster. Funnily enough, what you say about FinFETs being a "wasted effort" are easily applicable to PDSOI. If what you say about FDSOI is true though, then consumers will really benefit.

However, your statements just don't have any relevance to the discussion I was having. Sorry. :\

I'm just trying to point out that MPUs in devices that are in consumers hands right now, built on a 28nm process, are vastly behind 22nm in performance. Perhaps the best way of proving this, as I hinted at earlier with Altera, would be this chart:

For 28nm processes to be even close to 22nm would make Altera's claims here physically impossible. If we were to assume that 28nm and 22nm had equal performance, that would mean that 22nm -> 14nm would give an 100% boost in clock speed, which would be unprecedented. However, this is not the case, and 14nm is likely about 30%-40% faster than 22nm. This would imply that TSMC's 28nm trails 22nm in performance by 40-50%.

 

[TreVader]

It is absolutely baffling that you are attempting to disprove what I've stated with technologies that don't apply.

Samsung and Globalfoundries do use metal-inserted poly si on 28nm. It is useless to talk about theoretical what-ifs in scope of this discussion.

So what you're saying is that intel's bay trail architecture is so terrible, that even with a two node advantage they are still have 1/8th the (per core) IPC of Cyclone on 28nm?


I'm trying to understand why bay trail is so terrible on 22nm (it runs at 2.7Ghz, quad core still getting trounced by dual core 1.3Ghz ARM cores). It's abysmal and Core M should be on par with A8 or better, but then how is apple matching Intel with a two node disadvantage?

Obviously core performs well on 22nm, but it's still only about equal to cyclone on 28nm. It's one or the other, either bay trail is garbage or 22nm isn't all it's cracked up to be

 

[NostaSeronx]

Altera chose 14-nm FDSOI. Altera did this campaign to make Samsung and GlobalFoundries adopt it faster.

http://www.eetimes.com/document.asp?doc_id=1262895

Samsung and GlobalFoundries knows what Altera really wants. A high-margin low-volume customers at a dual-source foundry. That 14-nm deal I posted in the Carrizo thread at GlobalFoundries is Altera. http://forums.anandtech.com/showpost.php?p=36799107&postcount=361

 

[III-V]

So what you're saying is that intel's bay trail architecture is so terrible, that even with a two node advantage they are still have 1/8th the (per core) IPC of Cyclone on 28nm?


I'm trying to understand why bay trail is so terrible on 22nm (it runs at 2.7Ghz, quad core still getting trounced by dual core 1.3Ghz ARM cores). It's abysmal and Core M should be on par with A8 or better, but then how is apple matching Intel with a two node disadvantage?

Obviously core performs well on 22nm, but it's still only about equal to cyclone on 28nm. It's one or the other, either bay trail is garbage or 22nm isn't all it's cracked up to be

You're making hard claims, yet you have no data to back them up. This seems to be a consistent flaw with your arguments.

Altera chose 14-nm FDSOI. Altera did this campaign to make Samsung and GlobalFoundries adopt it faster.

http://www.eetimes.com/document.asp?doc_id=1262895

Samsung and GlobalFoundries knows what Altera really wants. A high-margin low-volume customers at a dual-source foundry.

"Watt said in his presentation that 14-nm FDSOI could give a 35 percent performance improvement compared with 28-nm bulk planar CMOS at the same switching power or a 32 percent lower switching power at the same delay time."

This pins 14nm FDSOI as being competitive with Intel's 22nm process, not their 14nm process.

Also, nowhere in your article does it state that Altera "chose" FDSOI; they've played with it, is all. Finally, this article was published before Altera ended up announcing that they had chosen Intel as a partner.

 

[TreVader]

Broadwell is presumably going to keep up with 11.5W Haswell-Y. But compared to fanless ARM, Broadwell will blow its competition away.

I don't know if that's true in Apple's custom core case, at least not in IPC.

Core has a much higher performance envelope than ARM and they draw more power too. Core is not very power efficient at all when compared to ARM, but maybe that will change with broadwell

 

[TreVader]

You're making hard claims, yet you have no data to back them up. This seems to be a consistent flaw with your arguments.

It's logically impossible for bay trail to be a good architecture while 22nm provides (according to you) a two node advantage.


You make a lot of hard claims about a process lead, while Intel currently is sitting on a node half node loss to TSMC....

I don't know if you understand logic, but it's a pretty simple deductive argument.

 

[III-V]

It's logically impossible for bay trail to be a good architecture while 22nm provides (according to you) a two node advantage.


You make a lot of hard claims about a process lead, while Intel currently is sitting on a node half node loss to TSMC....

I don't know if you understand logic, but it's a pretty simple deductive argument.

What can be asserted without evidence can be dismissed without evidence. Seeing as you've provided none, I have no choice but to discard what you are saying.

 

[TreVader]

What can be asserted without evidence can be dismissed without evidence. .

Who told you this? You obviously have no idea what deductive or inductive logic is. Thanks tho.

Insulting other members is not allowed here.
Markfw900


The evidence is in your own statements. Your own sentiments (that bay trail is a decent architecture and that 22nm is two nodes ahead of 28nm) are logically opposed, because we already know that 28nm SoCs easily out perform bay trail on 22nm.


"You can explain that!" - Bill O'Reilly

 

[III-V]

Who told you this? You obviously have no idea what deductive or inductive logic is. Thanks tho.

That's a quote from Christopher Hitchens.

The evidence is in your own statements. Your own sentiments (that bay trail is a decent architecture and that 22nm is two nodes ahead of 28nm) are logically opposed, because we already know that 28nm SoCs easily out perform bay trail on 22nm.

If you can't back up what you're saying, you shouldn't be saying it at all. Frankly, your refusal to provide evidence for your claims is rather disrespectful.

You made the first assertion, that Intel is lagging their competitors. Yet you have no data to prove it. The burden of proof is on you.

"You can explain that!" - Bill O'Reilly

The quote is "you can't explain that," and it's an extremely embarrassing quote at that.

 

[TreVader]

That's a quote from Christopher Hitchens.
If you can't back up what you're saying, you shouldn't be saying it at all. Frankly, your refusal to provide evidence for your claims is rather disrespectful.

You made the first assertion, that Intel is lagging their competitors. Yet you have no data to prove it. The burden of proof is on you.
The quote is "you can't explain that," and it's an extremely embarrassing quote at that.

It's embarrassing that you don't understand basic logic. That's embarrassing, and I would stop posting here now if I were you... I don't think I could handle being that out of touch w reality.

Insulting other members is not allowed here
Markfw900


You've outed yourself as somebody who doesn't have any insider info. You've been corrected multiple times, which is fine, if you can make arguments without evidence. You obviously don't have any evidence that isn't contrived and wrong, so are you gonna stop talking?


Intels bay trail lagging behind Apple A7 is well documented. Google iPhone 5s review lol, do I need to explain further how to learn things on the Internet? Bay Trial is competitive in one way: MT CPU. Its abysmal in GPU and even worse than that in ST.


And its called a typo. You see, cellphones have this thing called "autocorrect"...

 

[TreVader]

May have disappointing but at least it was on schedule. For as delayed as the 3770K-equivalent Broadwell on desktop is going to be when it finally gets here, we ought to be expecting more of a tock-level performance bump than a mere tick-level performance bump that IB brought.

But would you rather have a 5% improvement in 12 months or a 15% improvement in 15?



Looking at the intel ARK the 4650U looks like a beast. If they can fit that into a macbook air, I'm buying another one.

 

[Arachnotronic]

Looking at the intel ARK the 4650U looks like a beast. If they can fit that into a macbook air, I'm buying another one.

The 4650U *is* in the latest MacBook Air.

Per Apple:

1.4GHz dual-core Intel Core i5 (Turbo Boost up to 2.7GHz) with 3MB shared L3 cache

Configurable to 1.7GHz dual-core Intel Core i7 (Turbo Boost up to 3.3GHz) with 4MB shared L3 cache.

According to ARK, 4650U is 1.7GHz base, 3.3 GHz Turbo

 

[TreVader]

The 4650U *is* in the latest MacBook Air.

Per Apple:



According to ARK, 4650U is 1.7GHz base, 3.3 GHz Turbo

Full feature set too!


Well, looks like I'm out $1899 :awe:

 

[ams23]

Core M should be on par with A8 or better

What a silly statement to make. The CPU and GPU performance of the Core M SoC is ~ 2-3x better than Apple's A8 SoC. There is simply no comparison here.

Note that for the mobile market, perf. per watt is the most important metric, while perf. per MHz (aka IPC) without looking at power consumption is not very relevant except for an academic discussion.

Apple's Cyclone and Cyclone-enhanced CPU cores are quite power hungry, relatively speaking, compared to most other ultra mobile CPU cores. The same is true for Core M CPU cores, but Core M's CPU/GPU performance is already miles ahead of Cyclone-powered A7 and A8 SoC's too.

 

[witeken]

Planar is flexible and cheap.

FinFET is only 3% more expensive according to Intel, which is absolutely nothing compared to single vs multiple patterning vs EUV.

Planar is low leakage and high performance.

Yes, at 130nm a decade ago. Not when all your electrons are quantum tunneling through your single nanogate, so a better gate is needed; a Tri-Gate.

FinFETs are just a small short-term fix, to a non-problem. It is wasted effort and it doesn't even do what it is promised to do.

Okay, so an armchair engineer thinks he knows better than Intel itself how to spend billions of dollars on R&D. Intel, Samsung, TSMC and GlobalFoundries must be ridiculous for not seeing how much superior planar xtors are!!1

 

[witeken]

It's logically impossible for bay trail to be a good architecture while 22nm provides (according to you) a two node advantage.


You make a lot of hard claims about a process lead, while Intel currently is sitting on a node half node loss to TSMC....

I don't know if you understand logic, but it's a pretty simple deductive argument.

TSMC marketing team: we're 5 years behind Intel, but fortunately most people don't know how semiconductors work, so we'll just skip a few node and call our 20nm+FF node 5nm.

Does this mean to your logic that Intel's 14nm is 3 nodes behind TSMC?

 

[Roland00Address]

A better look at the Yoga 3 Pro's Hinge
Mobile Geek's unboxing of the Yoga 3 Pro

Looks like they are using a custom usb3 port as a charger with a a 20v 2 amp current.

 

[Arachnotronic]

Full feature set too!


Well, looks like I'm out $1899 :awe:

Normally I'd try to pull somebody off the ledge of buying a soon-to-be EOL laptop, but realistically, it doesn't look like a Broadwell based MBA is coming anytime soon.

I'd guess February or March since it'll probably be based on BDW-U.

Enjoy your new laptop!

 

[Hans de Vries]

I'm just trying to point out that MPUs in devices that are in consumers hands right now, built on a 28nm process, are vastly behind 22nm in performance. Perhaps the best way of proving this, as I hinted at earlier with Altera, would be this chart:

For 28nm processes to be even close to 22nm would make Altera's claims here physically impossible. If we were to assume that 28nm and 22nm had equal performance, that would mean that 22nm -> 14nm would give an 100% boost in clock speed, which would be unprecedented. However, this is not the case, and 14nm is likely about 30%-40% faster than 22nm. This would imply that TSMC's 28nm trails 22nm in performance by 40-50%.

But Altera itself atributes the 2x improvement mostly to it's entirely new HyperFlex Architecture:

The Stratix 10 HyperFlex Architecture Advantage
The HyperFlex architecture is the new, groundbreaking core fabric architecture for Stratix 10 FPGAs and SoCs. This architecture provides an innovative approach to overcome the limitations of conventional architectures such as: ever increasing bus widths, routing congestion, and interconnect delays. This results in a level of performance and power efficiency not possible with a conventional FPGA architecture, designed to meet the demands of the most advanced applications in the networking, communications, broadcast, military, and compute and storage markets.


Maximizing IP Core Performance with Stratix 10 FPGAs and SoCs
The HyperFlex architecture allows Altera to optimize its high-performance soft IP core portfolio to deliver 2X performance within the programmable core of Stratix 10 FPGAs, including:

• Altera’s optical transport network (OTN) IP portfolio, running at 350 MHz in previous generation FPGAs, achieves over 700 MHz performance with Stratix 10.
• Altera’s 400 Gigabit Ethernet IP reduces bus size from 1024-bits wide data in Stratix V, to 512-bits wide in Stratix 10 devices with a resulting 2X the performance gain thereby maintaining throughput while significantly reducing area utilization.

 

[witeken]

But Altera itself atributes the 2x improvement mostly to it's entirely new HyperFlex Architecture:

Look what I got from doing this simply altera intel 14nm Google search:

Intel offers a true die shrink with its second-generation 14 nm Tri-Gate process, relative to alternative FinFET technologies. As a result, Altera will deliver unmatched performance, power, density and cost advantages with its next-generation FPGAs and SoCs.
[...]
For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption.

Altera Achieves Industry Milestone: Demonstrates FPGA Technology Based on Intel 14 nm Tri-Gate Process, April 23rd