Leakage will increase at smaller geometries. However, changing the physical design of the transistor can mitigate this or possibly even temporarily move leakage backwards for a smaller geometry.
The changes you mentioned are done to combat increased leakage. However, changes applied appropriately can reduce leakage; there is not enough data to say anything about the total absolute leakage as applied in the transistor (other that saying the leakage will be more dominant at lower geometries).
Picture it this way. Imagine a process on X nm without any of the recent technologies that reduce leakage. Now imagine that same X nm process with major overhauls to reduce leakage. Say the chip 'leaks' 2-3x less (this is completely made up and is a dummy number to try and prove a point). Now imagine a smaller node with those advanced leakage combatant technologies. Despite being a smaller node with more (theoretical) leakage, the new transistor design may result in a transistor with less overall leakage than at the larger geometry non-refined process.