More bad assumptions. I would like nothing more than to have the data you are looking for as it's fascinating data. I just haven't seen any even remotely rigorous testing that we could use to draw these conclusions. I'm not saying you are wrong. Just that you are drawing conclusions from incomplete data.
We'll hopefully see more relevant data when the BDW-U and desktop processors come out when we have a slightly more applicable comparison.
Seems odd that Broadwell only "partially" decode h265 through igpu when upcoming snapdragons will fully decode it.
No real hevc hardware decoding until Slylake seems a long way.
It's not like hevc is mainstream yet but still.
Yes so basically if you buy a core M now, it will be less efficient in decoding hevc than upcoming snaps. For tablets etc it matters for battery life i guess.
So the slides are fake
Seems odd that Broadwell only "partially" decode h265 through igpu
A mistake in a slide does not automatically mean it's a fake, ask AMD.
That s not bad assumption, BDW need substancialy higher voltage at 2.6 than Haswell, when squared (power follow a square law in function of voltage) the ratio is higher than the theorical reduction in parasistic capacitances allowed by a node shrink, this latter parameter will not compensate enough for the higher voltage, indeed intel stated that the current 14nm used for BDW core M is to be replaced by a new process.
Lets look at something that could cause the behavior you are seeing which has virtually nothing to do with the process in the way you are thinking.
During design, you time your circuits from A->B etc... to make sure the data you need, gets to where it needs to go in the time allotted. These are characterized in simulations before you attempt to manufacture them from the data provided by the fab. This is true for Intel or Qcom or anyone who does circuit design really.
Now, at some point you'll have either a characterization of circuits which turns out to be overly optimistic (or pessimistic which is another discussion entirely). Most of the time you'll have enough timing margin on these paths. However, if this happens on a path that you are unable to speed up with your allowed knobs, a potential "fix/workaround" is to boost the voltage on the domain which can help correct for the slowness of the path. These types of things tend to be improved in later steppings of a product as they are low hanging fruit. I'm not saying that this is the case here.
Now, the situation listed above isn't really a problem with the process per se. The fets in Core M could indeed be faster and lower leakage than the old process but with simply the voltage+frequency information you'll never know. I have no idea what really is the cause of the data points you are showing. Nor do you.
Something you could potentially look at and draw conclusions on, is the entire design efficiency (process+design and compare to power+work done) as it's something you can measure more accurately. However, singling out "inferior transistors / inferior process" is something you can not do with your current data set.
Good points but this doesnt really apply in this case as it s not a completely new design, it s an iteration of an existing uarch, as such its building blocks are well characterised no matter that the process has been shrinked.
Second point is that we re not on extreme conditions where a part newly designed could struggle to reach the expected speed, we are at 2.6GHz, that is a relatively low frequency, so if a voltage boost is needed at this clock rate then it means that the process is sluggish, to summarize i think that they didnt get the expected conductance at a given voltage, hence the boosted voltage (transconductance not high ).
More assumptions. Using "new process node" and "well characterized" without having a not between them is just flat out wrong. You are massively underestimating the complexity involved.
Why is it so hard for people to admit they don't have enough data to draw conclusions? "I don't know" should be in any educated person's vocabulary.
Good points but this doesnt really apply in this case as it s not a completely new design, it s an iteration of an existing uarch, as such its building blocks are well characterized no matter that the process has been shrinked.
Along with "I was wrong"."I don't know" should be in any educated person's vocabulary.
If we're talking a tick where the process spec is getting rolled out, how can you say it's "well characterized" unless you mean "it's logically MOSTLY well defined but physically (area/timing/power) not well defined until the process spec rolls out"
Because they have the tools to extract their process characteristics out of real silicon, hence simulations will be accurate even at the transistors level, routing characteristics extraction is accurate by the definition, in principle there will be acceptable prevision of the circuit behavior, unless the process does not yield the expected results, be it in transistors characteristics or more likely for characteristics dispersion, this latter case will often require an higher voltage if it s too high.
Are we talking as if we were designing a "tick" project for the first time or something else? Maybe I missed a couple posts earlier. Process specs from test chips sort of go like:
*** Ignore the below if I completely missed your point.
If we're talking about tick-project (and clearly I'm speaking with a design bias and egging on the process guys)
1) Process test chip returned this, it's kind of fubared but we think we can deliver this, run with these specs.
2) Ok, so we made some progress, but RC delays are a little worse than we expected, run with these new specs.
3) Ok, we're pretty sure this is what things will look like, run with these new specs.
and occasionally...
4) Tape out happened, holy crap, you need to use these revised specs, please fix everything.
So... what are we talking about?
"We were confirmed twice that this PCN is actualy announcing un new stepping of BDW-Y, the F stepping, due to changes in the 14nm process".Par deux fois, on nous a confirmé que ce PCN annonce en réalité un nouveau stepping de Broadwell-Y, le stepping F, lié à des changements sur le process 14nm.
Because they have the tools to extract their process caracteristics out of real silicon, hence simulations will be accurate even at the transistors level, routing caracteristics extraction is accurate by the definition, in principle there will be acceptable prevision of the circuit behaviour, unless the process does not yield the expected results, be it in transistors caracteristics or more likely for caracteristics dispersion, this latter case will often require an higher voltage if it s too high.
Leakage is too high with the current revision of intel's 14nm FF
Process need modifications for the chip to work as projected, a new stepping, using said modded process, will be released as soon as possible.....
That s what Intel stated, they didnt talk of redesigning the chip itself, yet there are tons of people who refuse to admit this, hence the never ending discussion about what is publicly known, anyway first time is see some Intel supporting members denying Intel s official statements, not talking of you of course.
http://www.hardware.fr/news/13891/idf-stepping-f-core-m.html
"We were confirmed twice that this PCN is actualy announcing un new stepping of BDW-Y, the F stepping, due to changes in the 14nm process".
I think that it s clear enough.
I don't understand this person. Does anyone understand this person? 30% less efficient than 22nm. You are straight up stating this.
He's a lunar-landing conspiracy theorist, so it's really not much of a stretch for him to believe that Intel would take such a massive step back. :awe:
It's best to just ignore him.
Any news from Best Buy?
Ah, now I'm caught up. What you said is a possibility since the nature of stepping work outside bug fixes is to do small refinements to design or process anyways. However as a counterpoint, you can't really get a process to process comparison based on the final voltage/frequency result since design has timing/power optimized the design for the target frequency for a given process assumption. If that assumption was wrong, you end up with a very suboptimal design.