MHz Pkg J Score IA J GT J GT Temp
HD5500 750 14.5W 741 1.4W 3.6W 61C
HD4600 750 21.5W 652 0.8W 10.6W 78C
Look at the pic. The IA cores are using 1W and the GT cores are using 4W yet the package power is using 15W. 15W -4W -1W = 10W. What in the package is using the 10W?What do you mean with other 10W? It's a 15W SKU.
Look at the pic. The IA cores are using 1W and the GT cores are using 4W yet the package power is using 15W. 15W -4W -1W = 10W. What in the package is using the 10W?
Running furmark 1.15.1.0 at 640x480 Windowed on the HD5500 of the i7-5500U
Seems to be about 10W unaccounted for, cache? Not much drawn by either the IA or GT cores as can be verified by the low temps. 795points vs 820 points on HD4600 at 950MHz. Unfortunate the HD5500 is throttling, might have to limit the clocks a few hundred MHz less to try and get a better idea.
HD5500 Pkg Pwr 18-15W, GT cores 6-4W, IA Cores 4-1W, GT Temp 67C
HD4600 Pkg Pwr 28W, GT cores 16W, IA Cores 8W, GT Temp 87C
Yeah, the thermals for the HD4600 suck. The IA cores take about 4 times as much power to generate similar core temps.
EDIT:
Okay, clock for clock for the HD5500 and HD4600 a 14% improvement with the HD5500U at 33% less power. IA Clock 2.9GHz, Uncore clock 2.7GHz, GT Clock 0.75GHz.
Code:MHz Pkg J Score IA J GT J GT Temp HD5500 750 14.5W 741 1.4W 3.6W 61C HD4600 750 21.5W 652 0.8W 10.6W 78C
Can you do a 3dmark11 (P) run?
The problem with 3DMark and the 5500U with a 15W limit is that it throttles due to power limiting so the result is IMO inconclusive, please bear that in mind.
With discrete card disabled.
http://www.3dmark.com/3dm11/9214844
@Enigmoid, the CPU is configured to run maximum turbo unless it is power limited, clock modulated or thermally throttled irrespective of Windows power plan. No where near thermal throttling but the power limit is a problem. Yes, the integrated graphics max is 950MHz with option of unlocked bins to ~2.8GHz . Not that it would get even close to that. The edit I added to that post was with the integrated graphics maximum performance set to 0.75GHz so throttling was not a problem.
Linpack 11.2.1. 2 threads at 2.6GHz to keep it at 15W. Max package power 15.1W, IA Core power 13.8W temp 76C.
Impressive performance compared to the 11.5W TDP Haswell-Y predecessor, more than 50% faster @ 3DMark Cloud Gate (and 3x faster than Bay Trail). CB 11.5 score roughly matches the 5Y70-based Yoga 3 Pro. Let's see how the new revision (Core M-5Y10c, 5Y31, 5Y51, 5Y71) performs in a proper design like this.
That's no better than 5Y10. That's also verified by reading Helix 2 user reviews in TabletPCReview forums.Elitebook's Geekbench 3 score of 3,814 fell behind such Core i5-controlled contenders as the XPS 13 (5,153), the Thinkpad Yoga (5,057) and the Macbook Air (5,393), and our 4,165 ultraportable normal.
There are so many ways to change the performance of a CPU these days it makes things not so simple. There was a change from 3rd Gen to 4th with the way that the CPU handles C-State wake up and the CPU can be made through HW registers to treat any P-State as a request for full turbo thereby negating Windows power plan in respect to CPU performance states.I guess its changed then for newer CPUs. I generally thought that power saver mode reduces the clock to idle speeds (none or little turbo), balanced kept it at idle or stock speeds and performance kept the CPU idle at max turbo (not the entire chip but the cores that need it). That's been my experience with a 3630qm. Obviously that has changed.
Interestingly, scaling is 2x instead of BDW-Y's 2.2X. Any guess on the reason for that?Transistor Count 1.9 Billion is written on this slide for 2+3 BDW, they compared it to 1.3B for Haswell U @181 mm².
I know that BDW-Y has 1.3B transistors; it was sarcastic, since you didn't give a source.Regarding your link maybe Intel made an error at IDF, they possibly mixed up the number for Core M and 2+3 ULT. Core M at launch was specified at 1.3 Billion. http://www.extremetech.com/wp-content/uploads/2014/09/intel-core-m-broadwell-y-die-diagram-map.jpg
Makes sense.The IDF slide mistakenly paired the BDW-U 2 + 3 transistor count with the BDW-Y/BDW-U 2+2 die size.