Anyway, I'm not seeing much frequency increase at the same TDP yet for Broadwell 14 nm compared to Haswell 22 nm so far. So far everything points to a frequency wall having been hit after all, so that newer nodes no longer provide much higher frequencies.
14nm Cherrytrail ATOMs will have more CPU throughput and higher iGPU performance than Dual Core (2C 2T with GT1 or perhaps even GT2) Broadwell SKUs.
The best 15W U base went from 1.7 Ghz to 2.2 Ghz. The best 28W U base went from 3 Ghz to 3.1 Ghz. Both have lower turbos, which could be just simply because of the problems Intel's had with 14 nm.
It was not in regards to whether or not we've hit a frequency wall -- it was explicitly in regards to the regression that took place with moving from 32nm -> 22nm. The prediction, made by Homeles, is that Broadwell-K will have the same or better average maximum achievable overclocks on air, compared to Sandy Bridge-K. So if Sandy Bridge-K can hit 5.0 on average, Ivy Bridge hit 4.8, Haswell hit 4.6... Broadwell will bring us back up to 5.0 or better.Anyway, I'm not seeing much frequency increase at the same TDP yet for Broadwell 14 nm compared to Haswell 22 nm so far. So far everything points to a frequency wall having been hit after all, so that newer nodes no longer provide much higher frequencies.
Makes sense given that every node companies like TSMC claim spectacular transistor performance increases. I wonder how to reconcile that with the behavior of interconnects. To me it seems interconnects are the biggest issue since individual silicon transistors can clock at dozens or even hundreds of GHz (at least based on switching times, which are in the picosecond range or so).It is absolutely the case that frequency isn't scaling as well as it used to, but progress is still being made. We likely won't see a significant bump until we're in the post-silicon era.
Makes sense given that every node companies like TSMC claim spectacular transistor performance increases. I wonder how to reconcile that with the behavior of interconnects. To me it seems interconnects are the biggest issue since individual silicon transistors can clock at dozens or even hundreds of GHz (at least based on switching times, which are in the picosecond range or so).
Sorry for my inexperience but can you point me somewhere I can learn more about what youre talking about? I know transistor basics but dont understand the trait and property differences between the interconnect and the transistors.
Thanks Sorry of off topic
I have little doubt the interconnect issue will be addressed soon as well. Believe it or not, not having EUV is holding back frequency quite a bit as well.Makes sense given that every node companies like TSMC claim spectacular transistor performance increases. I wonder how to reconcile that with the behavior of interconnects. To me it seems interconnects are the biggest issue since individual silicon transistors can clock at dozens or even hundreds of GHz (at least based on switching times, which are in the picosecond range or so).
I don't really know a single source where you can learn everything. My (really quite elementary) knowledge comes from many places, like IEEE Spectrum, ExtremeTech, AnandTech, discussions on this forum, presentations, other random places, etc.
But the thing that people are talking about when they talk about transistor performance and power is Dennard scaling / Dennard's Law. Dennard's Law ended a decade ago because of quantum mechanics and physical limits: the gate length, which is responsible for frequency increases, became to thin so leakage became a major issue, and the gate oxide, which is the barrier between the gate and the channel, became too thin (on the order of atom monolayers) to be made smaller (the solution was to move to high-k materials so they could make it thicker while behaving electrically thinner, but the high-k hasn't become any thinner either, so maybe they'll have to go to ultra high-k).
I don't know how much you know, but I personally really like this presentation: https://www.youtube.com/watch?v=NGFhc8R_uO4.
I have little doubt the interconnect issue will be addressed soon as well. Believe it or not, not having EUV is holding back frequency quite a bit as well.
I have little doubt the interconnect issue will be addressed soon as well. Believe it or not, not having EUV is holding back frequency quite a bit as well.
Interconnects generally get worse as they are made smaller, no? EUV should allow denser interconnects to be made more cheaply (i.e. without expensive multi-patterning), but I would imagine solving the performance problems with respect to tighter interconnects has little to do with lithography...
It is simply a matter of scaling, literally.
As you make the wire smaller in width and height, the max current it can carry without creating reliability issues decreases.
Make the wire narrower (increase metal density by decreasing pitch) but keep it tall (don't decrease the metal thickness) and you will increase the capacitance, which slows down the circuit.
But, if you can scale down the pitch (make the wire narrower), the operating voltage, and the run-length then you can net-net to essentially negligible performance impact from the interconnect.
This is why you see more and more metal layers being added to process nodes over time. Adding metal layers increases cost and cycle time, but are the single-most easiest and straightforward way of alleviating interconnect induced bottlenecks.
You stop adding metal layers to your node when the incremental cost adder of adding metal layer N+1 to the stack no longer brings with it an acceptable incremental increase in performance.
In other words, there is a good reason today's process nodes don't have 30 metal levels (even though there are no technical problems preventing them from having that many), and an equally good reason they don't have just 3 metal levels.
To whatever extent the interconnect negatively handicaps or limits the operating frequencies of today's chips, that handicap and impact exists because of an economic argument and decision made by business leaders, not because of a technical or engineering limits put in place by process node development engineers.
(A real life example, as a process development engineer, myself and two other interconnect engineers successfully developed and implemented air-gap interconnects for the 65nm node, awarded patents and everything for them, but management elected to not implement them into production because the performance boost that came from the lowered capacitance wasn't something they felt the customer would be willing to pay extra for in the end product, so it was shelved for a later node...no technical limit, R&D was complete, but a decision was made based purely on economics and ROI. Please don't think I'm trying to take credit in any way for Intel's 14nm air-gap technology, I'm sure they either licensed the IP from TI or found other novel and unique ways to implement the same end result. I'm just excited to see air-gap technology finally making it into a consumer device! Can't wait to own one )
Broadwell's design would have been finalized well before that could have been implemented.Why leave out H.265 decode?
I was talking about CNT interconnects, really, or maybe something else.I don't think you're lying, but I'm hesitant believing people just on their words.
It was not in regards to whether or not we've hit a frequency wall -- it was explicitly in regards to the regression that took place with moving from 32nm -> 22nm. The prediction, made by Homeles, is that Broadwell-K will have the same or better average maximum achievable overclocks on air, compared to Sandy Bridge-K. So if Sandy Bridge-K can hit 5.0 on average, Ivy Bridge hit 4.8, Haswell hit 4.6... Broadwell will bring us back up to 5.0 or better.
Why leave out H.265 decode?
Arachnotronic, I take it you are of the opinion that Apple will stick with Broadwell for this retina macbook air? How do you think they will solve the thermal dissipation and battery life issues in such a tiny form factor, given how much smaller the battery must be if they are halving the thickness?
To give people a reason to buy Skylake.
Broadwell is clearly a late 2013/early 2014 design that got out way late. As I have said on this forum previously, it is very telling that Intel is sticking to the original Skylake schedule.
I think that Apple's industrial design teams are first rate and that's why they get paid the big bucks to solve these problems
They stuck the A7 into a slim 4" chassis even though that chip's maximum power draw was something on the order of 8W. And it wasn't a throttling mess in that chassis either!
I could see Intel debuting sky lake early in this MacBook Air. Broadwell will not cut it.
But I think I'm right about the A9 rMBA.
You gotta admit, two weeks ago I was told I was smoking something when I suggested this in the Broadwell thread. I'm sure you commented too. Now people are changing their tune... Slowly.
This is gonna be big if I'm right.
This is gonna be big if I'm right.
Although this would be great for Intel's mobile group, I doubt this.
That said...do note that Intel does use these chips for Celeron/Pentium, so who knows...
Yields are obviously a big part of the process, especially if it leads to having Intel to pull back clock speeds because they aren't hitting the targets.
Now I think about it I'd have GLADLY seen how x86-license-equipped Nvidia would have fared against Intel. Imagine HD 5300 on a Windows Tablet costing $300 with X1. AMD seems like a goner, bring Nvidia against Intel. Potential mass market traded for a piddly $1.5 billion....intel settles with nvidia more money fewer problems no x86