Intel Broadwell Thread

[oobydoobydoo]

Agree overall but your post is not easily understable for whom does not have at least a basical formation.

All wirings cant be that shrinked, for high current you have to take account of electromigration, for signal related connections you have to take account of resistance that would increase the charging/discharging time constants of the driven devices.

Also Finfets have intrinsicaly higher input capacitance than planar, this was undoubtly compensated on their 22nm by a better transconductance that allowed to reduce supply voltage since a better conduction at a given gate voltage means higher Ion and the capability to charge the input capacitances faster.

I think that it s this part of their design that went underperforming, not that their process is bad but to me it s obvious that dynamic power is higher than with Haswell, i dont think that it s due to strain capacitances but to the transistors input capacitances as well as lower transconductance than expected, hence the higher supply voltage to increase gate voltage and hence Ion, this is correlated by the 12.7% higher voltage at 2.9GHz, indeed i have no other explanation for this voltage caracteristic.

How will Altera's products be affected by the 14nm process vs this chip? I am sure they are expecting excellent performance, will they get it?

 

[Abwx]

I don't really understand your explanation and I haven't really followed the discussion.

But if I understand correctly, apparently BDW has a 12% higher voltage for a given frequency, which flies in the face of

How's that possible? A smaller node should decrease voltage, right?

It could but higher voltage doesnt mean automaticaly higher power comsumption, i explain it to you before answering to Tuxdave since this will allow everyone to understand very easily what is discussed.

On the slide you posted the first parameter is called capacitance, to summarize these are parasistic capacitors that are inherently built in with the transistor.

Thoses parasistic capacitors act as some wheight attached to each transistor and they create an electrical inertia, that means that when you send a current to drive a transistor the capacitors will absorb this current and keep the transistor from being fed the command voltage until you have charged enough said capacitor, at this point the transistor input has reached a voltage high enough that the transistor start to conduct massively and drive the next transistors with their own attached parasistic capacitors.

Now if your process use higher voltage you can compensate by reducing the capacitance accordingly by the square or the voltage ratio, that means that if your voltage is 20% higher (a 1.2 ratio) the capacitances must be reduced by a ratio 1.2 x 1.2 = 1.44 to get the same efficency.

Now the parameter called leakage is extremely dependant of the supply voltage, if you want low leakage you have to design your transistor such that it start to conduct at a higher command voltage, the benefit is that the higher the threshold voltage at wich the transistor start to conduct the lower the leakage when the transistor doesnt conduct

You see, that s all trade offs here and there, often different process will be used depending of the usage, for high performance you want transistors that start to conduct with low command voltage as it allow high frequencies but this will increase leakage, for low power devices leakage is an important metric so it will be higher command (and hence supply) voltages but also less leakage and lower frequencies.

Edit : The slide doesnt contradict the 12% higher voltage to answer to your question.

Here's my thought process. At first glance, with a gate wrapping around a channel, it clearly looks like "more gate" and thus "more capacitance". But since the channel topology allows a much better current control, you can relax the gate capacitance (higher oxide thickness) and still end up with better current than planar. Who knows. It's not very obvious to me which way it's guaranteed to go. You may be right.

You may aslo be right, mind you, i did read a paper from Altera about specific process optimisations for their designs at TSMC, and they also have access to Intel process, they state that Finfets have much better transconductance but also substancialy bigger parasistic capacitances, i ll post the PDF if i can find it again.

As for the frequency-voltage curve, that's affected by process and design. Imagine a curve which represents all possibilities frequency and voltage design point that the CPU design team is targeting. If you pick one design (which represents the lowest voltage to hit that frequency) and start to adjust voltage/frequency from a fixed design (how much voltage do you need to hit a higher frequency, how much voltage can you drop for a lower frequency), that SECOND curve will always be suboptimal compared to the first curve. How's that for a plausible explanation.

You are right since starting from an optimum will forcibly yield a worse caracteristic when you move around this optimum, be it by excess or by default.

Finfets higher input capacitance mandate shooting for the lower possible voltage and to get this you have to :

Either decrease the transistor conduction threshold (Vth) but this will increase exponentialy leakage when Vth is decreased and this is not compatible with a design that wants to be low power like Core M.

Or you increase the transitor transconductance (gm) at a same convenient Vth but that s precisely what is difficult to achieve since moving this parameter require modding slightly the geometry or using different materials at some places, like germanium, and this will shift all other parameters including thoses that are already satisfactory, among other the sub threshold caracteristic wich define the leakage current.

 

[TuxDave]

I don't really understand your explanation and I haven't really followed the discussion.

But if I understand correctly, apparently BDW has a 12% higher voltage for a given frequency, which flies in the face of

How's that possible? A smaller node should decrease voltage, right?

Pardon this craptacular picture but:

Blue = Optimal design points for old Process A
Red = Optimal design points for old Process B

Orange = For a high frequency design point on old process A
Green = A high frequency design point on new process B
Maroon = A low frequency design point on new process B

Note: Don't take this graph too literally, I used MS Paint but it gets my point across.

 

[Abwx]

How will Altera's products be affected by the 14nm process vs this chip? I am sure they are expecting excellent performance, will they get it?

Dont know, i ll provide some infos once i find the links, let s start with this one that show that Altera is not relying on a single process :

http://www.tsmc.com/uploadfile/ir/BusinessRelease/Altera-TSMC E.pdf

 

[Phynaz]

It could but higher voltage doesnt mean automaticaly higher power comsumption

And yet you keep making up numbers saying it does.

You just powned yourself for the second time in this thread.

 

[Abwx]

And yet you keep making up numbers saying it does.

You just powned yourself for the second time in this thread.

You should read more accurately what i write, i know that it s not easy at first glance but you should make the effort as it s not difficult and this will prevent you from writing such posts.

If you can decrease accordingly the parameter called capacitance then it will compensate the higher voltage, this is clearly stated, the difficulty is that if you double the voltage you have to divide by 4 the capacitance, of course in real life it s not such amplitude but that give you an idea.

What i m assuming is that Intel didnt manage to decrease enough this parameter to compensate for the higher voltage.

The higher voltage is also necessary because their transistors do not conduct well enough when they are driven by a voltage that cant be higher than the supply voltage, that is, a transistor output cant supply a voltage higher than the supply voltage, and the transistor conduct in proportion of what is applied at its input, and all transistors inputs are driven by other transistors outputs.

If you have trouble understanding i can use an hydraulic or pneumatic equivalent to explain it in a more intuitive way, fawcets are a good analogy.

Edit : Do you even realize that if i was talking randomly Tuxdave would had already pointed the thing since he has knwoledge of thoses principles.?.

 

[Idontcare]

For the lack of a better thread,

Here's a great article, interview in fact, for one's reading pleasure. Topics include R&D, EUV, 450mm, 7nm.

http://semiengineering.com/one-on-one-dave-hemker/

Nice interview, nothing surprising discussed by Hemker but I'm thinking his comment on 7nm xtor may have come as a surprise to you?

SE: Let’s go back to logic. What will 7nm look like?

Hemker: Every time we are working on a new node, we want to make it as incremental as possible. People are not going out and saying: ‘I hope I can go out and change the transistor.’ So at 7nm, if you look at the transistor, it might be a scaled 10nm finFET. You will see germanium playing a bigger role, whether its silicon-germanium or germanium. That part must be worked out. It’s less likely you will see III-V in there, because I don’t think it’s needed at that node. In the backend, there will be some challenges just to continue that scaling. That may end up being more levels of metal. Or you may see more aggressive scaling in terms of the barrier layer seed. But I don’t anticipate any earth shattering changes, like when we went from planar to 3D finFET.

(^emphasis added)

If it's not needed at 7nm then surely it isn't being integrated into 10nm.

I doubt he'd even risk discussing or touching on the III-V comment if it in any way runs contrary to what he already knows his company is working on with Intel at those nodes.

 

[jdubs03]

Nice interview, nothing surprising discussed by Hemker but I'm thinking his comment on 7nm xtor may have come as a surprise to you?


(^emphasis added)

If it's not needed at 7nm then surely it isn't being integrated into 10nm.

I doubt he'd even risk discussing or touching on the III-V comment if it in any way runs contrary to what he already knows his company is working on with Intel at those nodes.

I think what it comes down to is in term's of nomenclature; Intel's 14nm process is closer to actually being 14nm, whereas TSMC and Samsung are like you know more like 20nm in terms of scaling. So this relationship could continue so that when he says 7nm, he could mean 7nm for the foundries, which could be equivalent to Intel 10nm.

Just throwing it out there. I think 5nm for Intel could be when they switch to nanowire/gaa and iii-v+ge. It would make sense that they would want to have new materials and structure for at least 2 nodes before a switch.

ala:

A delay would make their chart look like the pace of innovation has slowed (which it very well could have). We just don't know enough. But if it is revealed that 10nm is just a 3rd gen FinFET scaled lower, some people will be disappointed and it will demonstrate that Intel's process lead has shrunk.

 

[Dufus]

But if I understand correctly, apparently BDW has a 12% higher voltage for a given frequency, which flies in the face of

First of all AFAIK there is no way to physically measure the IVR voltages, only register values from the CPU, how accurate are they at providing true voltage?

Secondly these register voltages change significantly with temperature in HSW, about 50mV decrease for 60C increase at 24 multi on my i7-4700MQ. Perhaps a reason why a BSOD can happen with undervolting when coming off high load. Never got to test this on BDW but wouldn't be surprised if similar.

Power readings read from RAPL are estimates. Again, how accurate are they? Already posted earlier that these can be manipulated to show a package power of 80W show 0.5W.

A better way would be to measure power delivery to the CPU from board and take into account static as well as dynamic power. Perhaps it is the static power savings that allow overall package power savings to give increased performance per Watt.

Certainly BDW idle power looks impressive over HSW, not so much on full load.

 

[witeken]

Nice interview, nothing surprising discussed by Hemker but I'm thinking his comment on 7nm xtor may have come as a surprise to you?
(^emphasis added)

If it's not needed at 7nm then surely it isn't being integrated into 10nm.

I doubt he'd even risk discussing or touching on the III-V comment if it in any way runs contrary to what he already knows his company is working on with Intel at those nodes.

Well', I've got a few hypotheses.

First, what he is calling 7nm might be the foundries' 7nm, so that would correspond to Intel's 10nm. Intel has always been a node earlier (45nm HKMG, 22nm FinFET) as well, so it wouldn't be surprising if foundries started using III-V at 5nm.

Secondly, I don't think Intel will delay III-V. Intel has a nice Tick-Tock node cadence (new technology, 2nd gen), so they probably kept in the back of their mind that they would have to look at something for 10nm, which has been III-V for maybe up to decade now. If they can get III-V working, which seems plausible to me for such a long R&D, then why not?

Thirdly, I don't think Intel would allow him to lay out the company's roadmap.

I've got no way to test them, so they're just guesses. From an earlier interview:

SE: Some say the III-V materials [at 7nm] have been pushed out or delayed. Any thoughts on that?

Bohr: Other companies may choose to push out the adoption of III-V, because all of the problems have not been solved for the 10nm generation. Tool readiness doesn’t seem to be the issue. It’s mostly device physics.

Would they have went in such a silicene if 10nm was just a regular 14nm shrink?

 

[IntelUser2000]

I think what it comes down to is in term's of nomenclature; Intel's 14nm process is closer to actually being 14nm, whereas TSMC and Samsung are like you know more like 20nm in terms of scaling.

Other than the transistor vs. transistor density which Intel may or may not be right on, it doesn't matter because they insist on making designs that are significantly larger than ARM chips. So even if they had the density lead, its merely to allow their cores to be competitive, not be any better.

A delay would make their chart look like the pace of innovation has slowed (which it very well could have).

Don't think that chart is anything BUT marketing. How do we quantify 22nm having 3.5 years lead when Ivy Bridge/Bay Trail/Haswell all lose in perf/watt to 28nm ARM parts? It would be right to say they have 3.5 years lead in implementation, but wrong to say they have a lead(which translates into better products). It's like getting a hybrid car 5 years before competitors but achieving same fuel economy as the regular gasoline competitors.

 

[witeken]

Intel calls it technology leadership.

Does Intel have a multiple year lead with air gaps and FinFET? Sure, but it's just single part of the jigsaw puzzle that is the final product. In any case, there should be no denying that having that lead (which would result in a quite significant advantage when all the rest is equal, which we might observe with SoFIA later this year) is a good thing (from Intel's POV).

 

[IntelUser2000]

Intel calls it technology leadership.

Marketing talk.

Like the hybrid that doesn't have better fuel economy, or performance over gasoline engines, but having "technological leadership". I guess its more "exotic".

Best, and only way to show leadership in process is when products show it. Actually only against rather anemic competitors like AMD it seems they are really ahead.

Not so much in the current ARM-dominated world.

 

[witeken]

Marketing talk.

I strongly disagree. Technology is what underlies all products. The transistor a fundamental and very important device that underlies all of technology. So when a company gets a radical change of that transistor into the market in volumes 3 to 4 years before any other company in the world (with the improvements in power etc.), then credits should be given.

 

[Abwx]

Best, and only way to show leadership in process is when products show it. Actually only against rather anemic competitors like AMD it seems they are really ahead.

That s true only for the specific X86 parts of the big cores lines, thoses latter s GPUs have lower perfs/watt than AMD s, on the low power X86 segment AMD offering has no trouble competing Intel s perf/Watt prowesses, so no , they are not that ahead.

Edit : Computerbase have published their review :

http://www.computerbase.de/2015-02/intel-nuc5i3ryk-broadwell-test/

 

[EnamResu]

please anandtech, for the love of god

In reviews, such as this

http://www.anandtech.com/show/8986/intel-nuc5i5ryk-review-a-broadwellu-ucffpc-for-enthusiasts

Provide CPU load and GPU load power seperately, not like now (Prime+Furmark), so we can compare CPU power consumption over generations, right now this is impossible (different GPUs!).

 

[Sweepr]

So according to Computerbase:

Thanks to enhanced clock and the applications show the internal architecture improvements up to 28 percent greater performance than the Core i3-4010U. Come special instructions such as Quick Sync to convert videos for use, the differences are even much larger. Overall, shows that powerful jump at the same TDP of 15 watts, of the new and initially so troubled 14-nm process is possible. In some cases, the new Core i3 comes even to the Core i5 mini PC from the Haswell generation more than just dangerously close - and this NUC was the flagship of the last generation.

The Broadwell-U Core i3 is up to 28% faster than its Haswell-U Core i3 counterpart (more if we consider Quicksync). Looking at power consumption data (Intel BDW NUC vs Zotac HSW NUC) they use the same amount of power @ video conversion with a small advantage to the BDW-U NUC at gaming and a slight disadvantage @ video playback. Not bad at all for a Tick.

 

[frozentundra123456]

Finally with the dell xps 13 and this we are seeing sone decent improvements, although the AT nuc review showed little improvement.

 

[jpiniero]

The Broadwell-U Core i3 is up to 28% faster than its Haswell-U Core i3 counterpart (more if we consider Quicksync). Looking at power consumption data (Intel BDW NUC vs Zotac HSW NUC) they use the same amount of power @ video conversion with a small advantage to the BDW-U NUC at gaming and a slight disadvantage @ video playback. Not bad at all for a Tick.

That sounds about right considering the base clock increased on the best i3 from 2 to 2.5. The i5 and i7 didn't get that much of an increase.

 

[TuxDave]

Edit : Do you even realize that if i was talking randomly Tuxdave would had already pointed the thing since he has knwoledge of thoses principles.?.

Let's not break out the "absence of evidence is evidence of absence" now. If something takes too much effort to explain in a forum post I move on.

Anyways, there's a lot of basic EE terms being thrown around and applied in very weird ways that I don't really how to start. A separate thread in highly technical may be useful if you want to learn the basics before drawing conclusions.

Personally happy to see that people are getting a positive impression of Broadwell.

 

[Abwx]

Let's not break out the "absence of evidence is evidence of absence" now. If something takes too much effort to explain in a forum post I move on.

Anyways, there's a lot of basic EE terms being thrown around and applied in very weird ways that I don't really how to start. A separate thread in highly technical may be useful if you want to learn the basics before drawing conclusions.

Personally happy to see that people are getting a positive impression of Broadwell.

I m always willing to explain to people how things works on a simple fashion and i do not bother rewriting posts using simple analogies if asked to do so, i use a few tech terms only with people who have knwodledge of them.

That said there was an excellent article at AT about semiconductors that was accessible to about all peoples, and there s the forum to eventualy give explanations to memebers that would have problem grasping thoses basics.

Indeed i benefit from this thread to point that a transistor can be considered (very) grossly as an electrical equivalent of a faucet.

 

[Sweepr]

Fanless Broadwell-U by Shuttle:

Shuttle launches its first Broadwell fanless barebone PC

Taiwanese space-saving PC chassis specialist Shuttle has launched its first Broadwell-toting fanless barebone PC. The Shuttle DS57U 1 litre class barebone system includes the chassis, a motherboard, cooling system, power supply and an Intel Broadwell CPU pre-installed. All the purchaser needs to build a complete system is some RAM, a storage device and an OS.

Shuttle has chosen to equip the fanless DS57U barebone with an Intel Celeron 3205U dual-core processor (2x 1.5 GHz) with integrated HD graphics. This Broadwell chip, built upon the 14nm process by Intel, consumes less than 15W and requires only the passive cooling system as equipped by Shuttle. Due to the fanless cooling of the processor Shuttle says that the resulting completed PC should run "remarkably quietly," with the added bonus of less dust being sucked into the chassis by any fans. [...]

http://hexus.net/tech/news/systems/80934-shuttle-launches-first-broadwell-fanless-barebone-pc

And some new Broadwell-U Core i7 (5500U & 5600U) notebook reviews:

Acer Aspire E5-771G Notebook Review

http://www.notebookcheck.net/Acer-Aspire-E5-771G-Notebook-Review.136653.0.html

First Impressions: Lenovo ThinkPad T450s

http://www.notebookcheck.net/First-Impressions-Lenovo-ThinkPad-T450s.136641.0.html

Lenovo ThinkPad X250 Ultrabook Review

www.notebookcheck.net/Lenovo-ThinkPad-X250-Ultrabook-Review.136646.0.html

 

[coercitiv]

Lenovo ThinkPad T450s Ultrabook Review equipped with i7 5600U.

With synthetic tools the maximum power consumption can rise to just under 49 Watt. But once the TDP limit of the processor is reached after about half a minute, this value falls to about 30 Watt, which is typical for ULV hardware. Thanks to the generously sized 65-Watt power adapter, the battery (set) even charges quickly under full load.

Based on this we can could Turbo Boost Short Power Max for Broadwell ULV is around 30W. This data is in clear contradiction with the Acer Aspire V3 review which allegedly showed the unit mantaining full CPU / GPU clocks within a modest TDP setting.

It is impressive that even after a one-hour stress test (Prime95 and FurMark) none of the parts of the case exceeded 37 °C. In view of the low system noise, this hints on a highly efficient cooling system.

The Core i7-5600U also does not suffer from critical core temperatures and reaches a maximum of 65 °C (stress test) to 75 °C (only Prime95). Nevertheless, the chip needs to throttle slightly during combined CPU and GPU load (CPU clock: 1.5 GHz, GPU clock: 750 MHz) because of its low TDP, but this is normal in the ULV range. A benchmark ran immediately afterwards did not show any performance loss.

Looking at this machine and comparing with other OEMs, it's interesting to observe the effect that power management settings and even OS version have on battery life, even with seemingly very efficient hardware.

 

[SAAA]

Broadwell mobile quad-core Geekbench3 score:

http://browser.primatelabs.com/geekbench3/1649284

Base clock is really low so I think this is just a test device, turbo speeds unknown but knowing Broadwell isn't a big jump I'd say close to 2.6GHz.

 

[Nothingness]

Broadwell mobile quad-core Geekbench3 score:

http://browser.primatelabs.com/geekbench3/1649284

Base clock is really low so I think this is just a test device, turbo speeds unknown but knowing Broadwell isn't a big jump I'd say close to 2.6GHz.

Wouldn't that rather be Skylake? Model number of Broawell is 61 not 71.

EDIT: Forget that, it looks like Intel model number is more complex...