Intel confirms 3rd 10nm family, 7nm delay

[NTMBK]

Because we're at two-and-a-half years [this is in reference to the time it takes Intel to transition from one technology to the next] this gives us the ability to bring out a third wave of products on 14-nanometer so we can land a product family on a very healthy, mature [manufacturing] process.

That ends up being a good answer for us and a great answer for our customers because we can allow them to refresh their product lines with new [intellectual property] blocks and things like that.

And so that's the strategy at 14 [nanometer], and likely you're going to see the same strategy at 10 [nanometer].

http://www.fool.com/investing/gener...s-existence-of-1.aspx?source=iaasitlnk0000003

 

[ShintaiDK]

Not a surprise due to economics.

 

[witeken]

I paraphrase Brian Krzanich:

We'll always try to get back to 2 years.

But given the complexity only rises, not drops, it's I guess no surprise that 7nm won't go back to 2 years (although, they always talk about 2.5 years, so maybe they're overshooting a bit with those 3 year nodes).

So the probability of 3 generations per node is high, which is why they're preparing this 2nd Tock, but I think it's completely foolish to say that Intel knows for sure that it can't get 7nm back to 2 years.

No one knows that.

My opinion is that Intel probably sees that they still can't count on EUV. I mean, how many patterning layers do you need at 7nm without EUV? It's probably crazy.

 

[eton975]

Aren't there two real problems with EUV?

The first is that they only have ~50W lasers out at the moment (at least from what I saw at the ASML website), while DUV excimers are 100W+.

Isn't the second that literally EVERYTHING absorbs it, which means new mats for all the equipment need to be developed? So low power, combined with loss of energy, means a long scan time over those Cannonlake chips?

Have I got this right?

 

[witeken]

Aren't there two real problems with EUV?

The first is that they only have ~50W lasers out at the moment (at least from what I saw at the ASML website), while DUV excimers are 100W+.

Isn't the second that literally EVERYTHING absorbs it, which means new mats for all the equipment need to be developed? So low power, combined with loss of energy, means a long scan time over those Cannonlake chips?

Have I got this right?

1. TSMC/Intel have 80W, which gives like 40 wafers per hour (I'm reading that 250W will be necessary for 125WPH, so that's 2W per wafer). Although I'm reading they can get 1000 wafers per day, and that probably not with 100% uptime.

There's also a few other problems which you can read in the article, like availability.

http://www.eetimes.com/document.asp?piddl_msgid=345022#msg_345022&doc_id=1327056&page_number=1

2. They use mirrors.

 

[mrmt]

Given that Intel 10nm is supposed to inherit a lot of technology from the troubled 14nm node, I will be quite surprised if Intel can ramp it up on the proposed schedule and keep even this 3 years cadence.

 

[ShintaiDK]

My opinion is that Intel probably sees that they still can't count on EUV. I mean, how many patterning layers do you need at 7nm without EUV? It's probably crazy.

That's a good question. 14nm is 2-4, 10nm will be at least 4 all around. 7nm, 4-8?

With 14/16nm initial wafers was excess of 15000$. With 10nm it will be 25000+ and who knows with 7nm. 50000?

 

[eton975]

That's a good question. 14nm is 2-4, 10nm will be at least 4 all around. 7nm, 4-8?

With 14/16nm initial wafers was excess of 15000$. With 10nm it will be 25000+ and who knows with 7nm. 50000?

The CAD/routing guys at Intel must be having a total nightmare designing these chips.

 

[biostud]

is it tick, tock, tock or tock, tick, tick?

 

[Tsavo]

I told them to go 8nm, but nooooooo, they didn't listen.

 

[NTMBK]

is it tick, tock, tock or tock, tick, tick?

Tic-Tac-Toe

 

[Khato]

Tic-Tac-Toe

I'm still ever so disappointed that they shied away from that naming. It was awesome.

 

[witeken]

I'm still ever so disappointed that they shied away from that naming. It was awesome.

Tick-Tock-Toe.

Officially it's still called Tick-Tock.

 

[CakeMonster]

So, even for hardcore enthusiasts who upgraded their desktop cpu once a year, it is quickly getting pointless. Say that if one will now upgrade every three years, do we have any idea which of the 3 increments would bring the most useful tech/performance? Or are we completely in the dark WRT when in the tick-tick-tock cycle Intel will introduce various stuff? Just whenever its ready™?

 

[Unoid]

Tick-Tock-Toe.

Officially it's still called Tick-Tock.

So Intel is naming the process after a Round metal robot that protects the land of OZ?

 

[DooKey]

Given that Intel 10nm is supposed to inherit a lot of technology from the troubled 14nm node, I will be quite surprised if Intel can ramp it up on the proposed schedule and keep even this 3 years cadence.

Don't you think they will only push forward with what works as they go to 10nm? I wouldn't think they would reuse something problematic again.

 

[jpiniero]

So, even for hardcore enthusiasts who upgraded their desktop cpu once a year, it is quickly getting pointless. Say that if one will now upgrade every three years, do we have any idea which of the 3 increments would bring the most useful tech/performance? Or are we completely in the dark WRT when in the tick-tick-tock cycle Intel will introduce various stuff? Just whenever its ready™?

Intel has kind of stopped giving roadmaps. For good reason - the Skylake architect said they overhauled the chip twice during development. Which you would think would be a recipe for disaster, but that might be the norm now for Intel. So in a lot of ways they might not even know what might make it in a chip release until the very last second.

Of course if you are upgrading specifically for games, it might not really matter. There's only so much you can get out of an 8-core Jaguar...

 

[Ajay]

The CAD/routing guys at Intel must be having a total nightmare designing these chips.

What about the litho folks?! The masks must be unreal. A bag a physics tricks to shoot through a round hole to make a square peg and geometries far more bizarre than that.

 

[ehume]

Ivy Bridge > Haswell > Devil's Canyon. Tick, tock, hiccup.

Broadwell > Skylake > Kaby Lake. Tick, tock, hiccup.

Cannonlake > Icelake > Tigerlake. Tick, tock, tock or hiccup?
New microarchitecture? Or "refreshed" prior microarchitecture?

 

[Arachnotronic]

Tick-Tock-Toe.

Officially it's still called Tick-Tock.

Internally "tick-tock" died a long time ago, AFAIK.

 

[Exophase]

So, even for hardcore enthusiasts who upgraded their desktop cpu once a year, it is quickly getting pointless. Say that if one will now upgrade every three years, do we have any idea which of the 3 increments would bring the most useful tech/performance? Or are we completely in the dark WRT when in the tick-tick-tock cycle Intel will introduce various stuff? Just whenever its ready™?

Well if this is true about Kaby Lake..

http://www.fool.com/investing/gener...ing-the-biggest-improvement-intel-corp-i.aspx

Then the "Toe" seems like it's not worth holding out for. If it were more like Devil's Canyon then that may be different.

Intel may get more development mileage out of moving to a 1.5 year tick-tock cadence instead but that would be pretty devestating to their market timing.

 

[IntelUser2000]

So, even for hardcore enthusiasts who upgraded their desktop cpu once a year, it is quickly getting pointless. Say that if one will now upgrade every three years, do we have any idea which of the 3 increments would bring the most useful tech/performance? Or are we completely in the dark WRT when in the tick-tick-tock cycle Intel will introduce various stuff? Just whenever its ready™?

No one knows.

We can guess though. It seems Tick and Tock now offers similar improvements. I am guessing that they might have thought rather than having BIG improvements every few year, its better to have smaller improvements more often. That's probably better for the market too, because it makes it predictable. No waiting around for extra year when every year you get the same improvement.

That's in general the idea of Tick/Tock. Before it was a potentially BIG improvement every 5 years. But you leave room for competitors to attack you within that period. Also, chips are getting incredibly complex. So smaller improvements more often means less risks are involved. End of traditional scaling will probably not come with a noticeable bang. We'll see more and more of these articles.

Then the "Toe" seems like it's not worth holding out for. If it were more like Devil's Canyon then that may be different.

What's your opinion on the "2x128MB eDRAM" on the highest end Kabylake GPU then? I am pretty sure its not just two 128MB chip for double capacity and there was a reason for calling it "2x". I would also hope for their sake they would substantially(not 20-30%) boost GPU performance to be competitive with Polaris/Pascal/Zen APU.

 

[StrangerGuy]

No one knows.

We can guess though. It seems Tick and Tock now offers similar improvements. I am guessing that they might have thought rather than having BIG improvements every few year, its better to have smaller improvements more often. That's probably better for the market too, because it makes it predictable. No waiting around for extra year when every year you get the same improvement.

Diminishing real returns from fab costs, performance per transistor and software development costs to extract performance out of hardware = Triple brick wall of economics.

It's only the hopelessly naive media who believes the real computing world is purely all about how fast you can calculate pi to the billionth digit.

 

[Eug]

Well if this is true about Kaby Lake..

http://www.fool.com/investing/gener...ing-the-biggest-improvement-intel-corp-i.aspx

Then the "Toe" seems like it's not worth holding out for. If it were more like Devil's Canyon then that may be different.

Hmmm... That's exactly why I'm skipping Skylake actually.

I'm an end user who likes future proofed video playback options at low power in his laptops.

 

[cytg111]

I hate readling about upcoming pioneering technology being delayed.