Intel Confirms Skylake Xeon D in Early 2018

[Dayman1225]

Intel Confirms Skylake Xeon D in Early 2018

 

[NTMBK]

Skylake-SP core, as in the one with AVX-512 and rearranged cache hierarchy? Interesting! I had assumed that the D would get "consumer" Skylake cores for efficiency.

 

[jpiniero]

Skylake-SP core, as in the one with AVX-512 and rearranged cache hierarchy? Interesting! I had assumed that the D would get "consumer" Skylake cores for efficiency.

I guess they are doubling down on their HPC push. Doesn't really make sense otherwise.

 

[el etro]

Want it on 14+.

 

[IntelUser2000]

Skylake-SP core, as in the one with AVX-512 and rearranged cache hierarchy? Interesting! I had assumed that the D would get "consumer" Skylake cores for efficiency.

This kind of makes sense. If they were going to get 16 core parts on regular Skylake core, they would need to make yet another die. It's plausible even Broadwell Xeon D's were taking this route - repurpose a server die. As for AVX-512, they could just have one unit enabled, rather than two. Cannonlake is likely going to do the same thing, and we'll have AVX-512 on the Y chips!

Besides, the cache hierarchy is actually a benefit on server workloads.

 

[DrMrLordX]

Want it on 14+.

That's the process being used for all the other Skylake Xeons, no?

 

[el etro]

That's the process being used for all the other Skylake Xeons, no?

Still no. Is 14 vanilla based. AFAIK Intel will get straight to 14++ in 2018.

 

[DrMrLordX]

Really? Skylake-X is 14nm+, no? Skylake-SP is 14nm?

 

[IntelUser2000]

Really? Skylake-X is 14nm+, no? Skylake-SP is 14nm?

It's same. They heavily reuse their cores.

https://en.wikichip.org/wiki/intel/cores/skylake_sp
http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5730

 

[jpiniero]

The other problem is that the extra AVX-512 unit and L2 bloats the die rather significantly. I'm not sure how much bigger but easily enough that they surely would not go more than the 16 cores that Broadwell-D already has. Although... the extra stuff is clearly bolted on, and this was presumably done by design so it could be removed "easily".

 

[IntelUser2000]

The other problem is that the extra AVX-512 unit and L2 bloats the die rather significantly. I'm not sure how much bigger but easily enough that they surely would not go more than the 16 cores that Broadwell-D already has. Although... the extra stuff is clearly bolted on, and this was presumably done by design so it could be removed "easily".

The extra L2 cache shouldn't really impact the die size. Because they take part of the space taken up by the L3 cache and use it as L2 instead. It's an area saving measure like ganging up 2 AVX-256 units to make 1 AVX-512 unit.

https://en.wikichip.org/wiki/File:skylake_sp_added_cach_and_vpu.png

While the core shows a irregular shape, if you look at the actual core, its rectangular, just like every other CPU.

https://en.wikichip.org/wiki/File:skylake_(octadeca_core).png

Here's a regular Skylake die: https://en.wikichip.org/w/images/thumb/f/ff/skylake_core_die_(annotated).png/450px-skylake_core_die_(annotated).png

Another one with L3 cache in view: https://en.wikichip.org/w/images/th...die.png/500px-skylake_4x_core_complex_die.png

You can see that the L2 cache is right next to the L3 cache. If you make the die irregular as the picture shows, than the layout becomes very complicated.

So why do CPU manufacturers call what seems like an extremely simple change an architectural change? Well, think about this. They number in the billions of transistors. A single core is probably in the 50-100 million range. A seemingly simple layout change requires titanic amount of work.

 

[Arachnotronic]

Really? Skylake-X is 14nm+, no? Skylake-SP is 14nm?

Skylake-X is just a partially disabled, multiplier unlocked Skylake-SP. They're both 14nm+.

 

[Dayman1225]

Still no. Is 14 vanilla based. AFAIK Intel will get straight to 14++ in 2018.

Skylake X and SP are on 14nm+, Cascade lake is going to 14nm++ in 2018 yes.

 

[DrMrLordX]

Skylake-X is just a partially disabled, multiplier unlocked Skylake-SP. They're both 14nm+.

That's what I thought. El etro seemed to think Skylake-SP was 14nm (not 14nm+).

 

[jpiniero]

https://www.servethehome.com/platform-power-consumption-first-benchmarks-intel-xeon-d-2100-series/

Kind of confirms that the Skylake Xeon-D is nothing but the Skylake-SP LCC/HCC die plus the Lewisburg chipset on package in a BGA socket and not a real optimized design. Still, I guess it's better than nothing since it's obvious they needed something when Cannonlake wasn't going to be possible.

 

[IntelUser2000]

https://www.servethehome.com/platform-power-consumption-first-benchmarks-intel-xeon-d-2100-series/

Kind of confirms that the Skylake Xeon-D is nothing but the Skylake-SP LCC/HCC die plus the Lewisburg chipset on package in a BGA socket and not a real optimized design. Still, I guess it's better than nothing since it's obvious they needed something when Cannonlake wasn't going to be possible.

Here are the compared chips. I only included those that have similar Base and Turbo clocks.

16 cores
Xeon D: 2187, 2183
Xeon SP: 6130

12 cores
Xeon D: 2166 2163 2161
Xeon SP: 4116

8 cores
Xeon D: 2146 2145 2143 2142 2141
Xeon SP: 4110 4108 3106

4 cores
Xeon D: 2123
Xeon SP: 4112

The Xeon D chips use less power, are cheaper, and perform faster. In fact its quite a bit more efficient. You are talking 15-26W extra for Lewisburg chipset features. Some comparisons show 20-25W less at similar performance, some are 15% faster at 15W less power, some show 10% gain with 35W less power. That's quite significant. The non-trivial gains would have needed a lot of work to make it possible.

 

[24601]

Undervolted, Underclocked chips with lower artificial power limits use less power, news at 11.

100% chance that most OEM boards with them on it will be either relatively power unlimited with beefy cooling to simply make these cheaper Xeon SP skus, or super underspeced cooling paired with unrealistically low power limits to try to fit in atom-style form factors.

The main thing segmenting this from Xeon SP is the 3.0 ghz max turbo.

Realistically these will be pointless compared to simply deploying what you would have anyways unless you have an application that scales perfectly and/or are trying to fit a pricepoint with high speed networking support (which is exactly how they are segmented).

In any case, Xeon D Skylake is likely to destroy all of AMD's server hopes, as there isn't actually anywhere that AMD can fit their chips in the ecosystem when Intel is willing to sell so much (superior) silicon for so cheap.

 

[raghu78]

In any case, Xeon D Skylake is likely to destroy all of AMD's server hopes, as there isn't actually anywhere that AMD can fit their chips in the ecosystem when Intel is willing to sell so much (superior) silicon for so cheap.

AMD offers better perf/$ and perf/watt right now in servers. You are very uninformed in this topic. AMD has a scalable server architecture with the Zen core and Infinity Fabric. Formerly codenamed Snowy Owl AMD has the EPYC 3000 series lined up for launch later this month at Embedded 2018. This one is going to hurt even more for Intel

https://hothardware.com/news/amd-snowy-owl-platform-epyc-3000-series-embedded-socs
https://videocardz.com/74939/first-motherboard-for-amd-snowy-owl-epyc-embedded-3000-series-spotted
https://www.computerbase.de/2018-01/snowy-owl-amd-cpu/

Whats even better AMD does not artificially limit its processors in terms of memory speed for market segmentation purposes. All EPYC 3000 CPUs will support 4 x DDR4 2666 Mhz . Intel limits DDR4 2666 Mhz to the costliest SKUs .

https://www.anandtech.com/show/12409/intel-launches-xeon-d-2100-series-socs-edge

"Memory support for the processor line extends to 512 GB of DDR4 ECC memory, and includes both RDIMM and LRDIMM support. This comes through supporting four channels of DDR4, at two modules per channel. What is inconsistent however is the rated support of the processors: most of the cheaper processors only support DDR4-2133 memory, expect the quad-core Xeon D-2123IT, which does support DDR4-2400. Above this, customers will need to spend at least $1400 to get a minimum of fourteen cores to get either DDR4-2400 or DDR4-2666. For the higher speed, this is limited to the top two QuickAssist enabled processors, which also need to support 100 Gbps of QAT. These processors also have the highest TDP, having almost the ‘best’ of everything."

 

[24601]

Skylake-SP has higher memory performance and lower latency at each memory tier, along with more memory channels per actual chip.

This means that a Skylake-SP with DDR4-2133 is in reality faster than a Haswell-E with DDR4-3000 in memory performance.

The actual performance of each configuration isn't determined by the memory itself for the most part.

Anything over Ryzen (ie. Threadripper, Epic) also has gigantic latency penalties that dwarf the memory latency and speed in any case.

You would also be a dimwit to use expensive ram (LRDIMMs, etc.) on slow cpu SKUs anyways, as the memory cost dwarfs any SKU's cost by an order of magnitude or more.

And that's before you bring up the fact that the Intel chips also outperform all the AMD chips in all real-world workloads.

The reason why AMD's server skus have such limited deployment is due to these facts.

The Xeon D Skylake is simply the nail in the coffin.

 

[aigomorla]

The reason why AMD's server skus have such limited deployment is due to these facts.

No that is not the reason why AMD has limited deployment.
The reason why they had limited deployment was because Magny-Cours was not competition worthy of its Xeon counterparts at the time.

Also the fact that Intel had a monopoly with most of the HW suppliers to use there chips like Dell, HP, Supermicro.

Your also completely ignoring the fact meltdown/specter is wrecking havok on all of Intel's chips, while AMD has a nice buffer.

Im pretty sure they did not fix this on Xeon - D which is why its gonna fail hardcore.
Who is going to trust a chip thats meant to handle security when there is a big door with a big arrow sign pointed at that door.
And to fix that door, you need to pay for performance, on again, a chip that has a set performance?

And your right the Xeon D is a nail in the coffin, for intel's own grave because not fixing Spectre/Meltdown on a chip post production, who is honestly going to want to deploy that?

 

[Burpo]

What? Skylake patch is out..

https://www.pcgamer.com/intel-releases-updated-spectre-patch-for-skylake-cpus/

https://www.pcworld.com/article/325...s-stable-spectre-patches-for-skylake-pcs.html

 

[aigomorla]

What? Skylake patch is out..

https://www.pcgamer.com/intel-releases-updated-spectre-patch-for-skylake-cpus/

https://www.pcworld.com/article/325...s-stable-spectre-patches-for-skylake-pcs.html

Im saying you need to patch it.
Its not a hardcore code.
So each time you redeploy you need to patch again, and again.

Also where typically the Xeon D niche falls into, is the area that is affected by the patch performance.

 

[jpiniero]

The Xeon D chips use less power, are cheaper, and perform faster. In fact its quite a bit more efficient. You are talking 15-26W extra for Lewisburg chipset features. Some comparisons show 20-25W less at similar performance, some are 15% faster at 15W less power, some show 10% gain with 35W less power. That's quite significant. The non-trivial gains would have needed a lot of work to make it possible.

I was comparing it more to Broadwell Xeon-D, but you could also throw in the Goldmont Atoms in some cases, and yes Epyc. It looks rather toasty. If 10 nm wasn't such a disaster you would have seen Cannonlake instead which would have been a much better product.

You have to remember that the mesh and the gimped L3 hurts performance at lower core counts.

 

[Gideon]

Anything over Ryzen (ie. Threadripper, Epic) also has gigantic latency penalties that dwarf the memory latency and speed in any case.
...
And that's before you bring up the fact that the Intel chips also outperform all the AMD chips in all real-world workloads.

That's just ridiculous. There are plenty of server workloads that are not the slightest sensitive to memory latency, only bandwidth (otherwise GPUs wouldn't work in any server workload at all).

And EPYC has more bandwidth, also in real-world workloads. It also has capability for more memory, which is a concern for some niche workloads.

In sparse matrix FP workloads (where you can't pack stuff neatly to use AVX512 units) EPYC outperforms Xeons significantly.

But yeah, of course DELL will go through all of this trouble, validating and announcing their EPYC line just to produce servers that are slower in every possible real-world workload

BTW one of the reasons EYPC was late (according to David Kanter from realworldtech), was because there was a problem with bootable NVM RAID. The fix was only released in the beginning of October. AMD only mentioned Threadripper, but actually EPYC was affected as well. RAID is a must for servers. So that's one of the reasons why they are only being announced now.

 

[24601]

All workloads that run faster on GPUs are not realistic workloads for CPUs (for blatantly obvious reasons).

It's as simple as that.