Discussion Intel current and future Lakes & Rapids thread

[tamz_msc]

The cores themselves are the result of a strategy which included that higher core count target. Calling them average in isolation is bizarre.

There is nothing wrong in comparing uarchs in isolation - just because Ice Lake struggles to clock beyond 4GHz doesn't mean that Sunny Cove isn't a good design. People liked to compare Bulldozer with Zen 1 and be impressed about the +52% IPC uplift - when there was nothing exceptional about it since one was a speed demon and the other was a brainiac design.

 

[tamz_msc]

Ice Lake AVX-512 Downclocking

Examining the extent of AVX related downclocking on Intel’s Ice Lake CPU

travisdowns.github.io

Looks like Ice Lake has minimal-to-nonexistent downclocking when running AVX-512 provided you do not run into power and thermal limits. Lets hope this holds true for Tiger Lake as well though I don't expect it to because 4.7GHz is pretty high for a ST turbo frequency.

 

[coercitiv]

There is nothing wrong in comparing uarchs in isolation - just because Ice Lake struggles to clock beyond 4GHz doesn't mean that Sunny Cove isn't a good design.

Sunny Cove was a good design for a mature 10nm node, it was not a good design for an uncertain 10nm node. Willow Cove may actually be a good design for it's time. Which should tell you a lot about the pitfalls of isolating the core from the system, as these two Cove cores are remarkably similar on paper.

 

[itsmydamnation]

There is nothing wrong in comparing uarchs in isolation - just because Ice Lake struggles to clock beyond 4GHz doesn't mean that Sunny Cove isn't a good design. People liked to compare Bulldozer with Zen 1 and be impressed about the +52% IPC uplift - when there was nothing exceptional about it since one was a speed demon and the other was a brainiac design.

Your like completely wrong here, there is nothing that really makes bulldozer a speed demon compared to Zen. Bulldozer was just a bad design and guessed the market completely wrong. What do you get if you take a Excavator cmt module, kill one of the cores and increase the ALU's from 2 to 4 along with associated dispatch and retire. You get pretty close to a Zen Core. Given that Zen 1 still functionally had XOP in its FPU should tell you the lineage.

Really Zen is an evolution of the components that make up jaguar and bulldozer in a core that had good design targets built by a team that appears to be well run. Even when doing a "clean sheet" design you dont re-invent the wheel.

 

[tamz_msc]

Your like completely wrong here, there is nothing that really makes bulldozer a speed demon compared to Zen.

David Kanter would like to disagree. Enough of AMD talk, let's keep this discussion on track.

 

[IntelUser2000]

Going back to Tiger Lake, I like what I'm seeing with Lenovo's Yoga line, the Tiger Lake design wins are quite appealing. However, availability starts with November 2020. Has anyone else announced models with Sep/Oct availability?

Well, the AMD version is October, and that's with Renoir. Lenovo has never been early with launches.

Lets hope this holds true for Tiger Lake as well though I don't expect it to because 4.7GHz is pretty high for a ST turbo frequency.

See, Icelake doesn't expand flops with AVX-512, it only supports the instruction. There's a cost associated with that too, but much less. Most SKL-X/SP cores do double Flops, which is the real cost for power.

Tigerlake for client is going to end up being the same. Based on Lakefield tests, I bet lot of applications don't support AVX2, nevermind AVX-512. By Intel 7nm, or 5nm maybe client can have two units.

Your like completely wrong here, there is nothing that really makes bulldozer a speed demon compared to Zen.

Bulldozer IS a speed demon. Not only many release articles covered it, the Chief Architect said it was made to "hold the speed", presumably perf/clock while raising clocks.

 

[Edrick]

See, Icelake doesn't expand flops with AVX-512, it only supports the instruction. There's a cost associated with that too, but much less. Most SKL-X/SP cores do double Flops, which is the real cost for power.

Maybe I missed this, but you are saying that Ice Lake client (and possibly Tiger Lake) only have a single AVX-512 unit, as opposed to the two on Sky Lake-X?

 

[jpiniero]

Maybe I missed this, but you are saying that Ice Lake client (and possibly Tiger Lake) only have a single AVX-512 unit, as opposed to the two on Sky Lake-X?

Dual 256, same as Skylake except it can fuse to 512.

 

[Thala]

The cores themselves are the result of a strategy which included that higher core count target. Calling them average in isolation is bizarre.

Looking at Zen cores, there is not single bit remarkable about them, so yes they are very average. There is also nothing in the microarchitecture, which makes them particularly suitable for high core count targets.
In summary, due to the innovative packaging, AMD scale up much easier than Intel can - which gives them an advantage - it is certainly not because the Zen core microarchitecture is this overwhelmingly outstanding.
I add here, that AMD also did the right decision of not jumping on the AVX512 bandwagon - because it is mostly dead silicon.

 

[JoeRambo]

Maybe I missed this, but you are saying that Ice Lake client (and possibly Tiger Lake) only have a single AVX-512 unit, as opposed to the two on Sky Lake-X?

Icelake-SP also has two, client Icelake has way more sensible dual 256 engine.

BTW Skylake-X in its original release in 2017 also had some SKUs with just 1 FMA, and only higher tier CPUs were with 2.

 

[tamz_msc]

See, Icelake doesn't expand flops with AVX-512, it only supports the instruction. There's a cost associated with that too, but much less. Most SKL-X/SP cores do double Flops, which is the real cost for power.

I'm pretty sure that AVX-512 on Ice Lake expends flops when running AVX-512 code, even though there exists only one FMA unit per core.

 

[LightningZ71]

This discussion, RIGHT HERE, is the reason that higher levels of AVX are only just barely beginning to be used. If we're having this much of an anurism about what unit in what configuration is in what product at what capacity with what level of support, why would developers bother targeting for it in a general sense. Of course there are going to be some highly specific, targeted packages out there that use it in certain scenarios, but, in general, for most use cases, its completely unused.

 

[TheGiant]

This discussion, RIGHT HERE, is the reason that higher levels of AVX are only just barely beginning to be used. If we're having this much of an anurism about what unit in what configuration is in what product at what capacity with what level of support, why would developers bother targeting for it in a general sense. Of course there are going to be some highly specific, targeted packages out there that use it in certain scenarios, but, in general, for most use cases, its completely unused.

IMO that is why Intel stopped trying to invent more AVX+++ and then invest tons of money and time to persuade companies to use it
instead they expanded SW universe from math folks (compilers, fortran libs) to video encoder engines and render engines
the same about linux
the Xe SIMT/SIMD concept is interesting especially because of this- distributing of what should be done with CPU and what with GPU
true APU is coming- the first one with tiger lake

 

[tamz_msc]

This discussion, RIGHT HERE, is the reason that higher levels of AVX are only just barely beginning to be used.

Not really. AVX is pretty much a requirement for getting decent performance on double precision workloads on the CPU. The higher the better, though not always. There's plenty of software make use of it depending on the domain.

 

[IntelUser2000]

I'm pretty sure that AVX-512 on Ice Lake expends flops when running AVX-512 code, even though there exists only one FMA unit per core.

And how do you figure may I ask? Throughput in Flops is determined by the vector units which is 1x512 bits in Icelake when using AVX-512 or 2x256 when using AVX2 or below. That's same as every other Intel processor all the way back to Haswell.

It's impossible to increase that number without adding more units.

the Xe SIMT/SIMD concept is interesting especially because of this- distributing of what should be done with CPU and what with GPU
true APU is coming- the first one with tiger lake

Maybe in HPC parts.

However in client they gave up the ability to do both back in Gen 9 because SIMT was better suited to GPUs, and while it afforded them flexibility, in the segment it was in that flexibility was useless. That allowed EUs to shrink by >25%. Good for them if they could downsize the EU while adding that back but I'm skeptical.

 

[tamz_msc]

And how do you figure may I ask?

The code used to investigate turbo behaviour does involve 512 bit FMAs.

 

[IntelUser2000]

The code used to investigate turbo behaviour does involve 512 bit FMAs.

The overall equation doesn't change man. AVX-512 in Icelake is only done by taking its double 256-bit units. In Skylake server and SKL-X for HEDT desktops there's actually a separate, and added single 512-bit unit, in addition to the 2x256.

It's actually similar to AMD's Jaguar supporting AVX, despite only having dual 128-bit FP units.

 

[Edrick]

I'm pretty sure that AVX-512 on Ice Lake expends flops when running AVX-512 code, even though there exists only one FMA unit per core.

Good article, thanks mate.

 

[Edrick]

The overall equation doesn't change man. AVX-512 in Icelake is only done by taking its double 256-bit units. In Skylake server and SKL-X for HEDT desktops there's actually a separate, and added single 512-bit unit, in addition to the 2x256.

It's actually similar to AMD's Jaguar supporting AVX, despite only having dual 128-bit FP units.

Do you know if Ice Lake SP is going to change that (similar yo Skylake SP/X)?

 

[Edrick]

BTW Skylake-X in its original release in 2017 also had some SKUs with just 1 FMA, and only higher tier CPUs were with 2.

That was proven to be incorrect. All Skylake-X parts had both AVX-512 units active. Only some of the Skylake-SP skus had a AVX unit disabled (Bronze/Silver/some Gold).

 

[tamz_msc]

The overall equation doesn't change man. AVX-512 in Icelake is only done by taking its double 256-bit units. In Skylake server and SKL-X for HEDT desktops there's actually a separate, and added single 512-bit unit, in addition to the 2x256.

It's actually similar to AMD's Jaguar supporting AVX, despite only having dual 128-bit FP units.

What has that got to do with the policy of downclocking when running AVX2 and above which has been present since Broadwell? My point was that Ice Lake client doesn't downclock on its own when running AVX-512 like Skylake-X/SP. Perhaps it's due to the latter having an extra FMA unit, but that doesn't mean that Ice Lake doesn't expend flops when running AVX-512 code which is what you claimed.

 

[IntelUser2000]

What has that got to do with the policy of downclocking when running AVX2 and above which has been present since Broadwell?

AVX downclocking wasn't thought to be a serious problem back then. It wasn't. With AVX-512 addition of FP power it dramatically increases the power requirements and clocking down started to become serious.

With Icelake client not having the extra vector unit it means we're back in the good old AVX/AVX2 days where turning on the latest ISA feature does not mean serious downclocks, at least for client.

You also misunderstood me. I'm saying compared to Broadwell, Skylake-client and ilk Icelake doesn't expand compute power. AVX-512 in SKL-SP/X does, and significantly. Icelake is also on 10nm which will improve the power behavior further.

Yes there's a power cost to AVX2, heck even the SSE units but not so much you had to seriously think of whether to implement the instruction(as with Skylake server).

Do you know if Ice Lake SP is going to change that (similar yo Skylake SP/X)?

Intel confirmed Icelake-SP has the additional 512-bit unit: https://www.anandtech.com/show/1598...-blog-next-gen-intel-xeon-ice-lakesp-930am-pt

(picture below 12:35PM EDT)

They said the downclocking issue isn't as bad and much improved compared to Skylake. No doubt a lot is due to 10nm. It will improve and someday its not illogical to think we'll have dual 512-bit support in client. But who knows though? By that timeframe maybe they'll put AVX-1024 in server and have the same issue.

 

[Edrick]

Intel confirmed Icelake-SP has the additional 512-bit unit: https://www.anandtech.com/show/1598...-blog-next-gen-intel-xeon-ice-lakesp-930am-pt

Your thoughts on if there will be a Icelake-X variant? I have been waiting for a reason to upgrade, and I cant bring myself to buy a Cascade Lake-X now. SR-X looks great, but we wont see that until 2022.

 

[IntelUser2000]

@Edrick Pretty good chance we'll see one. I can't see why not. As to when it'll arrive, server parts are a priority, so maybe summer?

 

[Markfw]

Your thoughts on if there will be a Icelake-X variant? I have been waiting for a reason to upgrade, and I cant bring myself to buy a Cascade Lake-X now. SR-X looks great, but we wont see that until 2022.

I hate to mention Rome, but why not consider this now ? Its most likely better than SR-X. Enough OT, if you want to consider it, start a thread with what you do, and we can compare them.

I will not bring it up again here....