It seems odd to me that there's so much back and forth regarding the release schedule of RKL-S when it was on roadmaps dating back to early 2018 as a Q1'21 launch. Are people just surprised that Intel confirmed it really is going to launch RKL-S in Q1'21 after all? I suppose it's not totally unreasonable to have lost faith in Intel's ability to launch anything new on time, even a backport to 14nm...
Same for ICL-SP. That was on Intel's June 2018 HPC roadmap as Q2'20 PRQ, H2'20 volume ramp. Intel confirmed during their recent earnings call that ICL-SP PRQ was underway during Q3'20 and volume ramp would take place in Q1'21. That's only one or two quarters behind their schedule from over 2 years ago for a product that we all knew was going to be a major ask of their 10nm manufacturing capabilities. ICL-SP was also shown in the 2018 roadmaps as only having a brief production window (3 to 4 quarters), so it's not terribly surprising that it won't have a particularly long market window. AFAIK, Sapphire Rapids isn't even in PRQ yet, so it should have at least some useful life, plus Intel has to figure out how to make big dies on 10nm at some point.
I also wanted to point out that once Intel committed to a dual-process roadmap, they're really stuck there until it makes economic sense to convert the bulk of their 14nm capacity to 10nm. They can't go all-in on TGL, RKL, ADL or whatever else because no matter which one you pick, the fabs will be capacity constrained and locked into a particular production schedule. They just have to ride it out as best they can until they have enough confidence to finally leave 14nm in the rearview.
And finally, now that DG1 has been formally unveiled, I wanted to point out that RKL was clearly *never* a chiplet design. It was a conventional monolithic die (including GT1 IGP) that could be paired with the DG1 companion die, which was a conventional PCIe Gen4 x4 dGPU based on Gen12/Xe-LP GT2. I assumed that they would at least be on the same package, and that would require using HBM2 as well. I should have realized that even that was too ambitious for a potentially high-volume product. DG1 simply has it's own LPDDR4X memory interface, which makes way more sense. That way they're free to do an MCP with a bog-standard substrate, or with separate packages as they did with Iris Xe MAX.