I don't have the faintest clue who you're talking about at SeekingAlpha, and don't care. Maybe you should stop reading that crap?
What you're saying is at least 50% false.
It is not just the previous CEO,
it's the current one as well.
Source below :
The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. Mass production of integrated circuit fabricated using a 7 nm process began in 2018. The process technology will be phased out by leading-edge foundries by...
en.wikichip.org
"the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. "
That would mean 202 MT/mm
"Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. "
That would be around 242 MT/mm.
Hence it would be 202- 242 MT/mm, with the upper bound actually being higher than what I posted.
Both of those numbers are far denser than anything TSMC or Samsung has said about their 5nm nodes.
This fits the pattern given that Intel's 10nm node is roughly the same density as TSMC's so-called "7nm" node.