Discussion Intel current and future Lakes & Rapids thread

[ondma]

Agree. Nevertheless, in spitting distance of the 6C Zen 3 5600H, 10% deficit in multi-core. A 6-core TGL-H would be absolutely killer. IDK what is up with this 4 core obsession from Inte.

I would actually consider scrapping my desktop for a 6 core TGL-H since it's multi-core would theoretically get near 8000 and best even a 10700 at that point.

View attachment 36399

Agreed, even a six core would be a very good product. Just a guess, but my feeling is that 10 nm yields are still making it difficult to get a good supply of anything more than a quad core. Hoping Alder Lake 8 core is not delayed.

 

[mikk]

Actually there's been rumors that S will be chiplets, with the IGP being 14 nm based. But it's a one chiplet type max kind of deal, you won't see a dual CPU chiplet for instance.

There is no such rumor and you will be wrong as usual.

 

[jpiniero]

There is no such rumor and you will be wrong as usual.

Do you think they will be able to actually yield something that big (if Alder Lake-S was monolithic) on 10 nm by the end of next year? That's why it makes sense.

 

[Hulk]

So hard to nail down IPC without good CPU data, like average effective clock from HWinfo.

But let's assume the Tiger Lake is running full single thread clock at 5GHz, which gives us 2.957 MHz per Geek mark.

Assume the 5950x is running full boost at 4.9 GHz for 3.067 MHz per Geek mark.

This give Zen 3 a 3.5% IPC advantage over Tiger Lake. Keep in mind that Rocket Lake will have lower IPC than Tiger Lake.

Tiger Lake (Willow Cove) would have brought Intel nearly to parity with Zen 3. Rocket Lake, which is Sunny Cove with Xe graphics won't get as close.

Of course it's not bad and Intel is certainly competitive, they are just a little behind in performance and way behind in power consumption.

There is place for them in the market if they are priced like 25% below comparable AMD parts.

 

[RTX]

If we assume RKL/TGL have the same IPC but TGL has higher L2/L3, would that help when running more background applications? Benchmarks almost always close everything.

 

[Exist50]

Do you think they will be able to actually yield something that big (if Alder Lake-S was monolithic) on 10 nm by the end of next year? That's why it makes sense.

Getting a tad tired of these rumors, so here. Alder Lake is monolithic. Tiger Lake H (real H series, not TGL-UH) hasn't launched yet, not because of yields, but because it simply hasn't made it to production yet.

 

[Bouowmx]

I'm hearing rumblings of 5.0 GHz Tiger Lake. Is it supposed to be the Core i7-11370H? It only reaches 4.8 GHz. Or another H-series processor?

 

[coercitiv]

This give Zen 3 a 3.5% IPC advantage over Tiger Lake. Keep in mind that Rocket Lake will have lower IPC than Tiger Lake.

Tiger Lake (Willow Cove) would have brought Intel nearly to parity with Zen 3. Rocket Lake, which is Sunny Cove with Xe graphics won't get as close.

Willow Cove is not higher IPC than Sunny Cove, at least according to Anandtech's analysis. The changes in cache architecture for Willow Cove positvely affect some workloads, while others suffer. The end result is close to IPC parity.

IPC improvements of Willow Cove are quite mixed. In some rare workloads which can fully take advantage of the cache increases we’re seeing 9-10% improvements, but these are more of an exception rather than the rule. In other workloads we saw some quite odd performance regressions, especially in tests with high memory pressure where the design saw ~5-12% regressions. As a geometric mean across all the SPEC workloads and normalised for frequency, Tiger Lake showed 97% of the performance per clock of Ice Lake.

 

[jpiniero]

Getting a tad tired of these rumors, so here. Alder Lake is monolithic. Tiger Lake H (real H series, not TGL-UH) hasn't launched yet, not because of yields, but because it simply hasn't made it to production yet.

So explain why the top UH is being branded i7 unless they were trying to hide the real Tiger Lake-H due to yield. A theoretical monolithic 8+8 Alder-S die would pretty big.

The UH makes a ton of sense because they can yield chips with defective Thunderbolt and IPU and mostly defective GPU but has all 4 CPU cores enabled.

 

[uzzi38]

I'm hearing rumblings of 5.0 GHz Tiger Lake. Is it supposed to be the Core i7-11370H? It only reaches 4.8 GHz. Or another H-series processor?

No, it's the i7-11375H that is 5GHz 1T.

Uses TB3.0 to get there.

 

[uzzi38]

So explain why the top UH is being branded i7 unless they were trying to hide the real Tiger Lake-H due to yield. A theoretical monolithic 8+8 Alder-S die would pretty big.

The UH makes a ton of sense because they can yield chips with defective Thunderbolt and IPU and mostly defective GPU but has all 4 CPU cores enabled.

Because there's still roughly a 2 quarter difference because actual TGL-H getting into devices and when this "TGL-H" will be. Intel aren't going to launch a -H lineup without an i7.

The real TGL-H isn't going to be much larger than TGL-U anyway. And yields are good enough now at least for dies of this size - good enough that lower binned products can make up the majority of defect chips anyway.

No need to worry about either.

As for ADL-S, that's a Q4 product, no need to worry about yields now. Not like the die would be that much larger either anyway. Atom cores are tiny - I imagine the two GCM cluster will probably be close to two GDC cores anyway.

 

[jpiniero]

As for ADL-S, that's a Q4 product, no need to worry about yields now. Not like the die would be that much larger either anyway. Atom cores are tiny - I imagine the two GCM cluster will probably be close to two GDC cores anyway.

But Golden Cove is going to be decently bigger than Willow if it's going to deliver the performance increase speculated. Throw in DDR5, PCIe5 and who knows what else.

 

[Exist50]

So explain why the top UH is being branded i7 unless they were trying to hide the real Tiger Lake-H due to yield. A theoretical monolithic 8+8 Alder-S die would pretty big.

The UH makes a ton of sense because they can yield chips with defective Thunderbolt and IPU and mostly defective GPU but has all 4 CPU cores enabled.

They seem to be pushing UH as something like high end iGPU gaming. I suspect we'll mainly see it in 13-14" gaming laptops, but that's just a guess. Personally don't think it makes much sense to begin with, but whatever.

The real TGL-H isn't going to be much larger than TGL-U anyway.

Eh... define "much".

Not like the die would be that much larger either anyway. Atom cores are tiny - I imagine the two GCM cluster will probably be close to two GDC cores anyway.

It's not Gracemont you have to worry about. But die size will clearly have to increase. If a GRT module equals a GLC core in size, then that still works out to an equivalent 10c GLC config for the S die. Then multiply the core area by GLC/WLC and add some for PCIe 5.0. That said, yields are probably not the biggest issue with Alder Lake.

 

[jpiniero]

They seem to be pushing UH as something like high end iGPU gaming. I suspect we'll mainly see it in 13-14" gaming laptops, but that's just a guess. Personally don't think it makes much sense to begin with, but whatever.

I'd have to think it's 32 EUs only; same as the real H die. That's why I mentioned yields as the enabled configuration is unique.

 

[shady28]

I'm hearing rumblings of 5.0 GHz Tiger Lake. Is it supposed to be the Core i7-11370H? It only reaches 4.8 GHz. Or another H-series processor?

I'll just say, I'd be disappointed and surprised if TGL-H retains the i7 moniker for a 4C part.

I really suspect the 3XX means it is an i5 part. This would correspond with naming conventions like i5-1035G1. If you look at the Intel naming convention, the "3" would be pretty low in the performance category.

This part's supposed naming convention is also counter to the new naming for ICL / TGL parts. 10370H is more like 9th /10th gen skylake derivatives.

In either naming convention though, ad "3" part is low to mid range. i.e. a 10300H is an i3 for skylake derived parts, and a 1035G4 is an i5 for Ice Lake while an 1135G7 is also an i5 for Tiger Lake.

An 1165G7 is an i7 for TGL, but the performance identifier is "6".

So if it retains any consistency at all with prior naming conventions, a part labelled 11370H would be an i5 or possibly even an i3.

 

[Hulk]

Willow Cove is not higher IPC than Sunny Cove, at least according to Anandtech's analysis. The changes in cache architecture for Willow Cove positvely affect some workloads, while others suffer. The end result is close to IPC parity.

If they positively affect some workloads that means clock-for-clock in those workloads Willow Cove will perform better and Sunny Cove. Therefore for those workloads wouldn't we say that Willow Cove has a higher IPC for those workloads? And if you averaged out multiple benchmarks on a clock-for-clock bases Willow Cove would come out ahead, thus having a higher IPC.
Not trying to be "smart" here I am really asking.

I thought if you "locked" the clocks of two processors, ran the same bench on both of them, the one that ran the bench faster had a higher IPC because it finished the task in less clocks than the other processor?

I'm confused?

 

[jpiniero]

There's an i5 11300h too. L3 is cut to 8 MB and has a lower turbo boost to 4.4.

The real H probably is 8 cores for i9 extreme and Xeon only and 4 cores for i7; with 6 cores being either i7 or i9 or both.

 

[Exist50]

I'd have to think it's 32 EUs only; same as the real H die. That's why I mentioned yields as the enabled configuration is unique.

No, 96EU. Maybe 80 for i5. Pretty sure it's fully or near fully enabled.

 

[uzzi38]

Eh... define "much".

Not enough to make yields an issue worth delaying TGL-H for.

It's not Gracemont you have to worry about. But die size will clearly have to increase. If a GRT module equals a GLC core in size, then that still works out to an equivalent 10c GLC config for the S die. Then multiply the core area by GLC/WLC and add some for PCIe 5.0. That said, yields are probably not the biggest issue with Alder Lake.

Die size will have to increase for sure, but again, not to the point where it'll cause issues with yields and especially not by Q4 next year.

 

[shady28]

There's an i5 11300h too. L3 is cut to 8 MB and has a lower turbo boost to 4.4.

The real H probally is 8 cores for i9 only and 4 cores for i7; with 6 cores being either or both.

Yeah, and not bad. This has to be their low end chip though, almost certainly an "i3", and clearly 4 cores. If this is what goes into cheap laptops next year, it'll be a good year.




Comet Lake i3-10300H

 

[uzzi38]

I'll just say, I'd be disappointed and surprised if TGL-H retains the i7 moniker for a 4C part.

I really suspect the 3XX means it is an i5 part. This would correspond with naming conventions like i5-1035G1. If you look at the Intel naming convention, the "3" would be pretty low in the performance category.

This part's supposed naming convention is also counter to the new naming for ICL / TGL parts. 10370H is more like 9th /10th gen skylake derivatives.

In either naming convention though, ad "3" part is low to mid range. i.e. a 10300H is an i3 for skylake derived parts, and a 1035G4 is an i5 for Ice Lake while an 1135G7 is also an i5 for Tiger Lake.

An 1165G7 is an i7 for TGL, but the performance identifier is "6".

So if it retains any consistency at all with prior naming conventions, a part labelled 11370H would be an i5 or possibly even an i3.


View attachment 36409

There are two TGL-H lineups that are going to launch. First is the one we've seen so far with the i5-11300H, i7-11370H and i7-11375H. Then later on we'll get skus with up to 8 cores. But that comes a while later.

 

[uzzi38]

If they positively affect some workloads that means clock-for-clock in those workloads Willow Cove will perform better and Sunny Cove. Therefore for those workloads wouldn't we say that Willow Cove has a higher IPC for those workloads? And if you averaged out multiple benchmarks on a clock-for-clock bases Willow Cove would come out ahead, thus having a higher IPC.
Not trying to be "smart" here I am really asking.

I thought if you "locked" the clocks of two processors, ran the same bench on both of them, the one that ran the bench faster had a higher IPC because it finished the task in less clocks than the other processor?

I'm confused?

No, Anandtech found that using SPEC - which contains a large variety of workloads - showed that on average there was a drop in IPC compared to Sunny Cove. They didn't just use a single workload for their analysis.

 

[Hulk]

No, Anandtech found that using SPEC - which contains a large variety of workloads - showed that on average there was a drop in IPC compared to Sunny Cove. They didn't just use a single workload for their analysis.

So what's the point of Willow Cove? Why did Intel create/release it if Sunny would have been faster on 10SF and required less die area?

 

[AMDK11]

So what's the point of Willow Cove? Why did Intel create/release it if Sunny would have been faster on 10SF and required less die area?

This can be a side leakage of data to which the core with the inbuilt cache system is very vulnerable, and the unused cache system is much less susceptible. For example, Bulldozer, Zen, Zen2, and Zen 3 have an inactive cache subsystem type that is very similar to WillowCove.

Sunny / CypressCove have the same subsystem as Skylake, with L2 containing the copy of L1 and L3 containing the copy of L2. The consequence is less effective cache capacity, but faster data exchange between the cores where the cores communicate and synchronize data at the L3 level.

The WillowCove x86 logic is the same as SunnyCove, except for a heavily redesigned, non-inclusive cache subsystem where L2 has no copies of L1 and L3 has no copies of L2. On the other hand, in fact, the capacities of L1, L2 and L3 add up, which can benefit a single core. The L2 cache, especially the L3 cache in WillowCove, is slower than in SunnyCove, which also affects the sensitive code in this account.

guess which cache system will be faster if core b) needs currently executing data from core L1 a)?

In non-Inclusive mode, where there is no copy of L1 in L2, you have to reach for much slower RAM more often, even if this data has just been processed. The large L2 and L3 are meant to partially compensate for this, but in inter-core communication where there is no copy of L1 even in L2, the cores must refer to L1 instead of L2 or L3, which causes downtime as the core has to make L1 available.

In Inclusive, copies of L1 data reside in L2 or even L3, so there are fewer situations where you need to access data directly from L1 or even from RAM.

 

[shady28]

This may be the first sighting of a 8C/16T TGL-H.

From this innocuous bug report for sof :

[BUG] Dell TGL-H Machine failed to load sof-tgl-h.ri · Issue #2662 · thesofproject/linux

Describe the bug I got a new Dell hardware. It's CPU information: lscpu.log The failed kernel log: journalctl-k.log Its acpi device info: _SB_.PC00.HDAS.SNDW.SWD0 0x000020025d071100 _SB_.PC00.HDAS....

github.com

This is reporting a bug in sof aka sound open firmware with TGL-H based Dell.

That aside, I went into the lscpu.log for the report and found the following.

High level : this CPU has 1.6Ghz base 4.8Ghz max. 10MiB L2 and 24MiB L3, along with 8 cores and 16 threads.

This is the cache setup matches what would be expected of a tiger lake 8C / 16T CPU.


Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
Address sizes: 39 bits physical, 48 bits virtual
CPU(s): 16
On-line CPU(s) list: 0-15
Thread(s) per core: 2
Core(s) per socket: 8
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 141
Model name: Genuine Intel(R) CPU 0000 @ 2.60GHz
Stepping: 0
CPU MHz: 1602.049
CPU max MHz: 4800.0000
CPU min MHz: 800.0000
BogoMIPS: 6220.80
Virtualization: VT-x
L1d cache: 384 KiB
L1i cache: 256 KiB
L2 cache: 10 MiB
L3 cache: 24 MiB
NUMA node0 CPU(s): 0-15
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l2 invpcid_single cdp_l2 ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves split_lock_detect dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq rdpid movdiri movdir64b fsrm avx512_vp2intersect md_clear flush_l1d arch_capabilities