MindFactory is selling 11700Ks for 479 Euros, and people are receiving them now.
Reviewers are going to be pissed if people buy it and post benchmarks. Albeit if those prices are legit Rocket Lake is not going to be all that interesting.
MindFactory is selling 11700Ks for 479 Euros, and people are receiving them now.
First benchmarks ran on recently bought 11700K are in on Hardwareluxx:
Are you under NDA as well?Hmm. I feel like I should say something more, but I'm struggling here.
5GHz on all cores for the 11700K? Why bother with the 11900K if this is true?
Because for 50% more money you get an easy 5.1Ghz on all cores (or something).
Geekbench 5 compared to my 5950x
Rocket prettymuch only wins in AES-XTS compared to Zen3
Zen 3 is still a beast but that comparison seems to show a strong 5950X vs a weak 11700K. Of course we don't know how they are clocked, but here's a comparison that shows things as being a bit more equal.
Hmm lower score runs higher clockspeed.. Something dont add up here.
4975mhz = 1746 points
4888 mhz = 1806 points
First benchmarks ran on recently bought 11700K are in on Hardwareluxx:
I realize I've asked this question before here but I really don't know why Intel spent all of that die space for the larger L2/L3 caches in Tiger Lake (Willow Cove)? The result was an average IPC decrease compared to Sunny Cove. They could have saved a little die space if they held it to 4 cores and/or possibly added a 6 core part.
I had thought that somehow it helps with the frequency gains they got. Also IIRC Golden Cove's cache sizes are the same as Willow Cove so maybe that had mostly to do with it.
Are you theorizing that when Sunny Cove gained approximately a 1GHz moving to 10SF that Intel deemed the current cache structure not sufficient? That's a good theory.
I realize I've asked this question before here but I really don't know why Intel spent all of that die space for the larger L2/L3 caches in Tiger Lake (Willow Cove)? The result was an average IPC decrease compared to Sunny Cove. They could have saved a little die space if they held it to 4 cores and/or possibly added a 6 core part.
Perhaps when the 8 core parts come out the larger caches will be necessary to feed the cores?
I just can't seem to wrap my head around it especially when they go back to Sunny Cove for Rocket Lake.
It may just be that the cache structure was intended to give better performance but the L3 speed was butchered to get Tiger Lake out of the door.
I’ve been pondering this as well, it seems that the L2 cache in Willow Cove had a very impressive upgrade. (2.5x increase in size for only a 1 cycle increase in latency) but the L3 cache change was so poor it’s actually caused a regression of performance in certain workloads.
I have several theories such as:
1. As jpiniero stated, Intel screwed up the L3 implementation and just rushed it out the door anyway (fairly unlikely)
2. The L3 cache change causes a performance regression in some workloads but an improvement in others, and the regressions are over-represented in AnandTechs review which skews the entire IPC average calculation. Other benchmarks show a slight IPC gain for Willow Cove of around 4%-5% (somewhat plausible)
3. The L3 cache change was inevitable as future core designs scale up. Intel had to bite the bullet and alter the way the L3 cache was implemented at some point in the near future, so they decided to do it now. Maybe it’s one of the those things in design and engineering where you have to go back a step and regress in the short term so you can move forward 2 or 3 steps in the future and gain more performance in the long term. (Personally I think this is the most likely)
Overall, looking at the changes in the CypressCove microarchitecture compared to Skylake, the average IPC increase of 18% should be on the bank because Intel did not introduce such large changes between the previous microarchitecture, which is quite intriguing.
Sunny / CypressCove
5-Way Instruction Assignment (Skylake 4-Way, Haswell 4-Way, SandyBridge 4-Way, Nehalem 4-Way, Conroe (Core 2) 4-Way)
Instruction re-queuing (OoO (ROB)) 352 entries in flight (Skylake 224, Haswell 192, SandyBridge 168, Nehalem 128, Conroe (Core 2) 96)
Scheduler 160 entries (Skylake 97, Broadwell 64, Haswell 60, SandyBridge 54, Nehalem 36, Conroe (Core 2) 32)
Register Files - Integer 280 entries + FP 224 entries (Skylake 180 + 168, Haswell 168 + 168, SandyBridge 160 + 144, Nehalem N / A, Conroe (Core 2) N / A)
Dispatch 10-Way (dispatch from scheduler (execution unit ports)) (Skylake 8-Way, Haswell 8-Way, SandyBridge 6-Way, Nehalem 6-Way, Conroe (Core 2) 6-Way)
X86 Skylake core 217 million transistors
Front-end
Cache L1-32KB 8-Way Instructions
µOP cache of 1536 entries
ITLB 8 entries (2M)
Allocation Queue (IDQ) 64 µOP / thread or 128 µOP single thread
LSD can detect up to 64 µOP loops / thread or 128 µOP single thread
5-way x86 decoder (1 comprehensive, 4 straight)
Back-end
Assignment of 4-Way Instructions
Instruction re-queuing (OoO (ROB)) 224 entries on the fly
Scheduler 97 entries
Register Files - Integer 180 entries + FP 168 entries
8-Way Dispatch (dispatch from scheduler (execution unit ports))
Execution Engine
3x FP-ALU (Arithmetic-logic-floating-point units (2x FMAC 256bit))
1x ALU (Arithmetic Logic Unit)
1x StoreData (data warehouse)
3x AGU (2x loading addresses, 1x generating addresses)
Memory subsystem
In-Flight Loads 72 entries (loading in flight with L1D)
In-Flight Stores 56 entries (in-flight storage to L1D)
L1-Data Cache 32KB 8-Way
Cache L2 256KB 4-Way
-------------------------------------------------- -------------------------------------------------- --------------------
X86 CypressCove core 300 million transistors
Front-end
Cache L1-32KB 8-Way Instructions
µOP cache of 2250 entries
Smarter prefetchers (smarter preselector)
Improved Branch Predictor
ITLB 16 entries (double 2M)
Allocation Queue (IDQ) 70 µOP / thread or 140 µOP single thread
LSD can detect up to 70 µOP loop / thread or 140 µOP single thread
5-way x86 decoder (1 comprehensive, 4 straight)
Back-end
Assignment of 5-Way Instructions
Instruction re-queuing (OoO (ROB)) 352 entries on the fly
Scheduler of 160 entries
Register Files - Integer 280 entries + FP 224 entries
10-Way Dispatch (dispatch from scheduler (execution unit ports))
Execution Engine
3x FP-ALU (Arithmetic logic floating point units (1x FMAC512bit or 2x FMAC256bit)) (in fact it is 1x FMAC512bit + 1x FMAC256bit)
1x ALU (Arithmetic Logic Unit)
2x StoreData (data warehouse)
2x AGU (loading addresses)
2x AGU (address generation)
Memory subsystem
In-Flight Loads 128 entries (loading in flight with L1D)
In-Flight Stores 72 entries (in-flight storage to L1D)
48KB 12-Way L1 Data Cache
Cache L2 512KB 8-Way