Not sure how schematic it is vs reality, but the fact they added 8 Gracemont cores rather than 4 Golden cores (guess estimating) for that area hints the contrary. They can't be that large or it would be pointless.
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They have a real small core architecture which is a much better fit, they don't need Skylake.
The small core decoders directly use most of the x86 instructions rather than changing them to internal instructions - continuation of what the original Bonnell Atom did.
It may perform like Skylake
It's not the addition of AVX-512 that makes the Core cores bloated. It's the ridiculous focus on clock speeds that's the issue.
ALD topping at a maximal 20% ST gain? The average IPC gains is thus possibly significantly lower. I expected the 20% figure to be an average IPC gain.
Nope, every Atom has its own internal uop mapping just like the big cores.
Fat chance, it will not be even remotely close.
There is no free lunch, you are not going to get performance without spending area... therefore all this talk of big core level performance from atoms is pure fantasy.
Intel's Atom Architecture: The Journey Begins
www.anandtech.com
You want a bet or something? Tremont is already at Ivy Bridge levels. Another 30% gets us to Skylake.
Do you know what makes that possible? Because ARM cores can do it.
Oh right, cause there's no such thing as optimization. That's why since Zen they beat Intel to a pulp in perf/mm2. And that's why M1 almost beats it in overall performance with again, a fraction of the size.
If it was just about the ISA, why does the GPU in M1 perform so fantastic in perf/mm2?
Because there are other factors such as: motivation, execution, optimism about the future and the project you are working at, which are all human factors not "ISA".
At least they're consistent:The title by Gamersnexus is a bit ruthless:
The main source of bloat is the area resources required to implement depth of execution speculation. If the CPU pipeline is designed appropriately for the target clock frequency there is no reason for an extraordinary area cost. There is no free lunch, you are not going to get performance without spending area... therefore all this talk of big core level performance from atoms is pure fantasy.
-The small core decoders directly use most of the x86 instructions rather than changing them to internal instructions - continuation of what the original Bonnell Atom did.
-Sunny Cove increases the L1 data cache, while in Gracemont it'll increase the L1 instruction cache. Likely the L1I increase helps with the doubled decode.
-Starting from Tremont, it uses dual cluster decode which according to the chief architect it saves space in comparison to the uop cache.
-Starting from Goldmont it also has a predecode cache. A massive 64KB on Goldmont Plus.
I expect Gracemont cores to be substantially bigger than Tremont, but they'll still be barely over 1mm2. The Tremont cores are like 0.7mm2. Sunny Cove core is 5-6x the size of Tremont, not 3-4x.
Obviously, 8+8 will not compete with 16 real Zen cores. I think the real target is 12 core zen performance. Hopefully, Intel will price AL to somewhat reflect this.Increasing L1i is a must to improve decode rate. Same with predecode L2 cache, a must for such architecture.
uOP cache ( as done by Sandy+/ZEN, not P4 ) while complex, it saves energy by not having to decode over and over again, at some point those savings + not having to have those massive decoder supporting structures wins over.
I feel like big part of Core bloat comes from sizing of various buffers: ROB, int PRF, FP PRF, uOP cache, branch prediction unit buffers, multi level I/D TLBs, TLBs that have variuos page sizes, store and load queues.
Atoms used to cut corners in all those structures and is making great use of diminishing returns of their sizing. For example large pages in TLB? Only added in Goldmont? 3 decoders? Also recent addition.
Combine these cuts with obvious cuts to execution resources, vector size support and caches sizes, ports and path widths => tiny die area is the end result.
Atom is more like "dial transistor budget to get performance targets they need" product. It's not like in 2014 it was a secret to them that having iTLB with large page support would help performance, or design of such TLB was beyond their capabilities. it was conscious decision to forgo better performance for die size savings.
What I don't share with You is optimism at performance targets. Honestly that hybrid 1+4 cpu was a disaster and that is understatement already. And it used those Tremont cores that have already dialed structure sizes up on 10nm a lot. But look at disastrous performance compared to other mobile CPUs in for example Cinebench R15? R20?
So Intel's Alder Lake 2xMT performance is very likely a pipe dream on 10nm, probably based on comparison with some hilariuos wattage constrained mobile CPU.
The desktop reality will be ~11 Golden Coves in Cinebench and waaaaaaay behind AMD 16 core cpus. And since it will struggle in poster childs of linear scaling, memory not-touching MT loads, the best way to use it will be disabling those Atom clusters and not having to deal with scheduling problems.
What I don't share with You is optimism at performance targets. Honestly that hybrid 1+4 cpu was a disaster and that is understatement already. And it used those Tremont cores that have already dialed structure sizes up on 10nm a lot. But look at disastrous performance compared to other mobile CPUs in for example Cinebench R15? R20?
Sure, any time. I love how people just throw around double digit gains like nothing. Here, ivybridge still 30% faster than Tremont in GB5:
What are you talking about? Firestorm cores are huge. Zen 3 CPU cores are 5mm2 apiece. We are not talking about massive size differentials here. You are right that optimization can make a huge difference. But it won't turn a 1mm2 core into a 5mm2 core.
And it used those Tremont cores that have already dialed structure sizes up on 10nm a lot.
Talking about IPC more than actual pure performance. Obviously Gracemont isn't going to clock to 5 Ghz. Surely there's some amount of density gain they could realize even if it lowers max frequency.
Lakefield had problems, yes. But complaining about rendering performance on a 7 W device is probably the worst possible argument you could make against Lakefield. Honestly who buys a laptop with low performance and long battery life with the intention of fast image rendering? That would be like a high-end restaurant buying their ingredients from McDonald's down the street, doing poorly, then complaining that therefore the McDonald's food could not possibly be successful.What I don't share with You is optimism at performance targets. Honestly that hybrid 1+4 cpu was a disaster and that is understatement already. And it used those Tremont cores that have already dialed structure sizes up on 10nm a lot. But look at disastrous performance compared to other mobile CPUs in for example Cinebench R15? R20?
It will be a success based on how much effort they put into it. Intel's 14nm would be a massive improvement for many designs. The majority of TSMC revenue comes from 16nm and older processes I think Intel's soon-to-be-spare 14nm could compete well in that space if they help potential customers get their designs working on the process.Plus they are going to try the foundry system again. Good luck with that.