Discussion Intel current and future Lakes & Rapids thread

[dmens]

No, it's not. 5 is considered very good in the industry for a complex soc. Intel's historically been slower.

LOL. Where I work now, heads would roll if we took that long.

 

[dullard]

AT article on a PCIe 5x4 SSD controller by Marvell. It's almost 10 W for just the controller though.

For most uses of drive controllers, the power is less important than the energy consumed per GB. That is because for most uses the controller isn't saturated at full power for more that a couple seconds at most.

In one second, the PCIe 5.0 Marvell MV-SS1331 can read 14 GB sequentially using up to 8.7 W. That is (14 GB/s)/(8.7 J/s) = 1.61 GB/J.
in one second, the PCIe 4.0 Marvell 88SS1321 can read 3.9 GB sequentially using up to 2.0 W. That is (3.9 GB/s)/(2.0 J/s) = 1.95 GB/J.

It is a slight step back in amount of data transferred per unit of energy, but it isn't much of a step back. And that is comparing their first to market PCIe 5.0 controller to their self-proclaimed most energy efficient PCIe 4.0 controller. 18% less power efficient for 3.59X more sequential read speed. Seems like a decent tradeoff.

 

[Exist50]

LOL. Where I work now, heads would roll if we took that long.

Making simpler chips obviously has a shorter turnaround. So now you have to either claim Intel's better than the industry, or that their timeline doesn't indicate further 7nm delay.

 

[dmens]

Making simpler chips obviously has a shorter turnaround. So now you have to either claim Intel's better than the industry, or that their timeline doesn't indicate further 7nm delay.

Heh, and how would you know where I work and the kind of SoC's I am working on?

Also your second sentence makes zero sense, since there are companies that tape out more complex silicon on a shorter schedule.

 

[Exist50]

Heh, and how would you know where I work and the kind of SoC's I am working on?

Also your second sentence makes zero sense, since there are companies that tape out more complex silicon on a shorter schedule.

Im making an observation of the industry standard for a complex modern SoC, and pointing out the implications of your own claim.

 

[dmens]

Im making an observation of the industry standard for a complex modern SoC, and pointing out the implications of your own claim.

Hope you realize Intel taking an obscene amount of time to bring silicon to market is not mutually exclusive with process problems.

 

[Exist50]

Hope you realize Intel taking an obscene amount of time to bring silicon to market is not mutually exclusive with process problems.

For the 3rd time, your own numbers are industry standard, if not better.

 

[dmens]

For the 3rd time, your own numbers are industry standard, if not better.

Having actually worked in this industry for almost two decades, gonna have to say you are dead wrong, as always.

 

[Exist50]

Having actually worked in this industry for almost two decades, gonna have to say you are dead wrong, as always.

Sure, sure. And Tiger Lake came after Ice Lake. And node scaling is a myth. At least we have your Gracemont claim to highlight eventually.

 

[dmens]

Sure, sure. And Tiger Lake came after Ice Lake. And node scaling is a myth. At least we have your Gracemont claim to highlight eventually.

I didn’t get a mea culpa from you on Rocketlake power efficiency, so I am not expecting one from you on Atoms clocking to 4ghz either.

 

[Exist50]

I didn’t get a mea culpa from you on Rocketlake power efficiency, so I am not expecting one from you on Atoms clocking to 4ghz either.

Oh please do quote what I said on Rocket Lake. Actually, you claimed it would never run at lower TDPs at all. We have the chips to prove that wrong today. But as is the habit of trolls, they quickly switch to the next topic.

 

[dmens]

Oh please do quote what I said on Rocket Lake. Actually, you claimed it would never run at lower TDPs at all. We have the chips to prove that wrong today. But as is the habit of trolls, they quickly switch to the next topic.

JFC, your dishonesty is just staggering. Power alone doesn’t matter at all. It is power/perf that matters. And RKL’s mediocrity in that aspect is self-evident. But here you are, talking about power in a vacuum, and clutching at some made up statement about how I somehow said RKL can’t run “at lower TDP”, because somehow you can’t lower the voltage and the frequency and have a slow but working chip. Yeesh.

Now you are going off about how I supposedly said that node scaling doesn’t exist, when what really happened was that I mocked your nonsensical linear extrapolations of node scaling and use of unmarked marketing slides.

And let’s not forget you actually claimed you have a EE degree. I showed mine, where is yours? Or are you just gonna flush your meds down the toilet and make more stuff up?

 

[Exist50]

Power alone doesn’t matter at all.

Well you were the one claiming it would be impossible for there to be lower TDP SKUs, so sounds like your problem, not mine. Back-peddling all the way back to "well it's not a good product so it doesn't matter what I claimed" is kind of funny though.

Now you are going off about how I supposedly said that node scaling doesn’t exist, when what really happened was that I mocked your nonsensical linear extrapolations of node scaling and use of unmarked marketing slides.

You mean those "nonsensical linear extrapolations" that are proven in silicon with TGL? You know, it's bold to pretend a product doesn't exist that one can go out and buy. Then again, you also claimed that product came before Ice Lake, so it's hard to tell if you know what it even is.

I showed mine, where is yours?

I have zero desire to pull mine out of storage to appease an internet troll.

 

[dmens]

Well you were the one claiming it would be impossible for there to be lower TDP SKUs, so sounds like your problem, not mine. Back-peddling all the way back to "well it's not a good product so it doesn't matter what I claimed" is kind of funny though.

Never said that, and you failed to find the quote when asked. I don’t talk about SKU’s, because I don’t care about SKU’s. What I did say was that your argument that RKL will be more power efficient than CML because it has the same TDP is a total joke. Because… you have no clue what TDP is. That I definitely did say.

You mean those "nonsensical linear extrapolations" that are proven in silicon with TGL? You know, it's bold to pretend a product doesn't exist that one can go out and buy. Then again, you also claimed that product came before Ice Lake, so it's hard to tell if you know what it even is.

Not even going to bother with this, since a dozen other posters on this thread called you out on this and all you could do is say it is “proven with TGL silicon” when you failed to normalize power and performance. And no, you just saying, “it has been taken into account” does not make it so.

I have zero desire to pull mine out of storage to appease an internet troll.

Pathetic.

 

[Exist50]

Never said that, and you failed to find the quote when asked.

Lying isn't anything new, nor do I care to put in the effort to deal with trolls, so I saved your Gracemont prediction this time. Pity it will take months.

What I did say was that your argument that RKL will be more power efficient than CML because it has the same TDP is a total joke.

Please do quote me. Go on.

Not even going to bother with this, since a dozen other posters on this thread called you out on this

This is called hand-waving, btw. A common tactic when one has no rational argument against a point. Indeed, when Gracemont can hit 4GHz, sounds like you'll claim the silicon is a lie, just as you're doing with Willow Cove now.

And with that, enough feeding the trolls for one day.

 

[dmens]

This is called hand-waving, btw.

Say what now? Citing other posters is “hand waving”? Are you high?

On that note, a more accurate example of “hand waving” is you saying “it has been taken into account” when other posters challenged your linear extrapolation without taking any other factors into account.

 

[IntelUser2000]

Guys.

Priorities please. Are we so spoiled in the western world that we have to attack each other in a forum about computer hardware? Really? Argue on, but be civil.

Oh, and engineers with PHDs and degrees can be wrong plenty of times. Just saying.

 

[itsmydamnation]

Man @Exist50 , do you believe the BS your sprouting ? Arm are releasing new A Core every year. Apple not much different, you have tenstorrent on the front page bring a 600mm SoC to market with what15 people , AMD is ~ 18months and at this point including consoles has almost as many SoC's with what 1/10 of the employees ( yes i know foundries etc). Unless all these places have lots and lots of teams running across the entire pipeline across multiple generations concurrently then @dmens has to be correct just from a design throughput perspective.

 

[dmens]

Oh, and engineers with PHDs and degrees can be wrong plenty of times. Just saying.

Well, he said I don't work in the industry so I obliged him, but he doesn't have the guts to reciprocate.

Anyways, insider story time. There was an institutional crisis inside Intel back in 2015-2016 on that exact topic of tapeout-to-market timeline. Intel suddenly realized the competition was going to market on B0 stepping silicon in less than a year after tapeout, largely because they had far fewer silicon bugs than Intel was used to having to deal with. Intel was also receiving a lot of criticism from customers on the large amount of post-market errata and bugs that customers themselves were finding, and this usually results in furious customers.

Unfortunately, they realized that the reason the competition was achieving this and Intel not was because of: Intel's ignorance of contemporary validation methodology, and the competition's execution excellence and very strict attention to detail. The first one is basically a lost cause, the next two Intel was poorly equipped to deal with due to the recent purge of senior engineering staff. LOL.

 

[RanFodar]

Unfortunately, they realized that the reason the competition was achieving this and Intel not was because of: Intel's ignorance of contemporary validation methodology, and the competition's execution excellence and very strict attention to detail. The first one is basically a lost cause, the next two Intel was poorly equipped to deal with due to the recent purge of senior engineering staff.

Sure, but can we see anything in the future that Intel will will come back from the stagnation and uncompetitiveness? After all, it is in the consumers' interest that they as a semiconductor and processor making company to innovate and have the choice for buyers for the best processors.

 

[Exist50]

Man @Exist50 , do you believe the BS your sprouting ? Arm are releasing new A Core every year. Apple not much different, you have tenstorrent on the front page bring a 600mm SoC to market with what15 people , AMD is ~ 18months and at this point including consoles has almost as many SoC's with what 1/10 of the employees ( yes i know foundries etc). Unless all these places have lots and lots of teams running across the entire pipeline across multiple generations concurrently then @dmens has to be correct just from a design throughput perspective.

I'm not sure if you're asking this seriously, but yes, those companies absolutely have teams working on multiple designs in parallel. A source for ARM's, if you want it.

Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm

www.anandtech.com

The main design centres for Cortex-A series of CPUs are found in Austin, Texas; Cambridge, the United Kingdom, and Sophia-Antipolis in the south of France near Nice. For the last two years the Cortex A73 and Cortex A75 were designs that mainly came out of the Sophia team while the Cortex A53 and more recently the A55 were designs coming out of Cambridge. This means that we haven’t seen any recent designs coming out of Austin and the last of the “Austin family” of CPUs were the A57 and A72.

Intel does/did the same with tick-tock and the Oregon and Israel design teams. AMD likewise has multiple CPU teams. IIRC, one in California, and one in Austin as well. Apple is known for having many teams even competing internally.

Having multiple teams working in a leapfrog fashion is absolutely essential to a yearly release cadence. But consider also that different stages of the project demand different skillsets. The architects largely finish their jobs before the post-Si team has started theirs. And derivative projects (e.g. Cezanne) are much smaller in scope than mostly new ones (e.g. Renoir).

Startups like Tenstorrent work for this example as well. You ever check out Nuvia's hiring page after the company went public? Lots of design and validation openings, despite the architects throwing out numbers. And for Tenstorrent itself, you can bet they grew their team as the project advanced.

 

[itsmydamnation]

I'm not sure if you're asking this seriously, but yes, those companies absolutely have teams working on multiple designs in parallel. A source for ARM's, if you want it.

ok i understand now, your either:
1. a ********* idiot
2. intellectually dishonest
3. dont know how to read/comprehend

i'll let you pick which one because your response has nothing to do with what i said.

Personal insults are not allowed in the tech forums.

AT Mod Usandthem

 

[Exist50]

ok i understand now, your either:
1. a ********* idiot
2. intellectually dishonest
3. dont know how to read/comprehend

i'll let you pick which one because your response has nothing to do with what i said.

You literally said:

Unless all these places have lots and lots of teams running across the entire pipeline across multiple generations concurrently then @dmens has to be correct just from a design throughput perspective.

Linking you to a source for the companies in question having exactly that is as direct an answer as possible. If you're unwilling to learn anything, why even participate in a tech forum?

 

[moinmoin]

Sure, but can we see anything in the future that Intel will will come back from the stagnation and uncompetitiveness? After all, it is in the consumers' interest that they as a semiconductor and processor making company to innovate and have the choice for buyers for the best processors.

Jim Keller in the interview currently on AnandTech's front page again clarifies his approach: Essentially picking people who can make a difference in their areas and ensure that they can do real work, not be hampered by bureaucracy and naysayers. The big question now is how successful he was with that at Intel, and whether this change of working culture is allowed to proceed and bloom in his absence. AMD seems to do very well since. With Intel we still have to wait for the fruits of this.

 

[eek2121]

Jim Keller in the interview currently on AnandTech's front page again clarifies his approach: Essentially picking people who can make a difference in their areas and ensure that they can do real work, not be hampered by bureaucracy and naysayers. The big question now is how successful he was with that at Intel, and whether this change of working culture is allowed to proceed and bloom in his absence. AMD seems to do very well since. With Intel we still have to wait for the fruits of this.

Based on his other quotes? He wasn’t. I feel like the message is clear. The bureaucracy was too much and he had other stuff going on, so he left. He left on seemingly good terms, which hints at the possibility of a return in the future when he gets bored and if Intel continues to bleed.