Discussion Intel current and future Lakes & Rapids thread

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dacostafilipe

Senior member
Oct 10, 2013
772
244
116
So they changed the strategy again and went with a Tick-Tock-Rename instead? /s

How often will Intel "realigning" itself with the industry in the future?

This is just to "calm" down shareholders and says nothing about Intel's performance in the future.

Not a fan!
 

lobz

Platinum Member
Feb 10, 2017
2,057
2,856
136
> Intel 7 is probably behind N4

> Intel 7 is probably around N5 but behind N5P

Uh, which one is it?

Anyway, I don't really mind the naming changes all that much. Although having to refer to 10ESF as 7nm now is just plain weird. And I don't expect Intel's 4nm to be measurably more dense than N5/N5P products, given how Intel tend to spam HP cells more than everyone else, with product densities tending to be smaller than the competition's (e.g. Lakefield compute tile is 49MTr/mm^2, despite being a die with no I/O)
Lakefield CD had to be that loosely packed to prove a point (of foveros actually working without catching fire)
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
Intel also revealed the GPU EU count for Meteor Lake yesterday:



Up to 192 EUs

Finally! SoC on package means with Foveros they moved the Northbridge effectively on-die, reducing power for mobile applications.

Let's hope they actually deliver the battery life improvement unlike Lakefield.

192 EUs itself isn't a big deal considering we'll see RDNA2 iGPUs with Remembrandt next year. Just keeping competitiveness that's all.
 

mikk

Diamond Member
May 15, 2012
4,183
2,220
136


So it really seems like Intel is launching ADL-S at the end of October (as MLID claimed).
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
Tremont cluster: 4.6-4.8mm2

I took a look at the Sapphire Rapids shot and annotations again. AMX takes nearly 1mm2. Then if you reduce the L2 cache to 1.5MB, the Golden Cove core in Alder Lake might end up being about 8mm2.

The L2 for the Gracemont cluster is 2MB. My rough estimate says Gracemont core ending up in the 1.3-1.5mm2 range. Skylake on 10nm is about 4mm2 so you get the idea.

If the dimensions are correct you can also estimate the die size. Alderlake's LGA1700 package is 42.5mm x 37.5mm.
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
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Intel is claiming a clear path to process performance leadership by 2025, but i don't see how that can be realistic
View attachment 47802

I mean they are behind both TSMC and Samsung in the race to GAA, and that is best case, if they can stick to their own roadmap this time.
View attachment 47803

If Intel can execute, they are closer than you think:

He seems to be hedging the bet that 2023 is possible, but 2024 is the most reasonable timeline.
This would be a similar time frame to TSMC’s 2nm process node which will utilize gate all around transistor architecture, likely in 2024.
 

jpiniero

Lifer
Oct 1, 2010
14,871
5,473
136
So it really seems like Intel is launching ADL-S at the end of October (as MLID claimed).

That's about as late as you can go with a launch assuming the actual release date is probably 2 weeks later. The real question is what the availability will be.
 

Shivansps

Diamond Member
Sep 11, 2013
3,873
1,527
136
The thing with those 192EU, they are going to be fast, maybe even faster than RMB, but the Intel problem as always is timing, by the time Meteor Lake shows up RMB should be on its way out, if everything goes OK for both AMD and Intel. Meanwhile, we are going to have, on desktop, the biggest IGP gap in history the second RMB shows up.
 

DrMrLordX

Lifer
Apr 27, 2000
21,842
11,199
136
Intel renaming their processes like that just seems stupid somehow. Now it's going to be difficult to understand what anyone has been saying about their 10nm and 7nm processes for, I don't know . . . years? Good job sowing confusion Intel.
 

uzzi38

Platinum Member
Oct 16, 2019
2,703
6,405
146
The thing with those 192EU, they are going to be fast, maybe even faster than RMB, but the Intel problem as always is timing, by the time Meteor Lake shows up RMB should be on its way out, if everything goes OK for both AMD and Intel. Meanwhile, we are going to have, on desktop, the biggest IGP gap in history the second RMB shows up.
Rembrandt will definitely be on it's way out, 2023 is competing vs Phoenix.

That being said, Phoenix sticks to the same iGP - next improvement there is with Strix Point in 2024.
 

eek2121

Diamond Member
Aug 2, 2005
3,063
4,299
136
What difference would standardized benchmarks make? Neither Intel's old names or the new names had any basis in physical reality, not for a long time.

When the node names did conform to physical reality everyone tried to scale by sqrt(2) every two years as that would double the number of transistors which fit Moore's Law and what ITRS dictated in its technology roadmap for semi equipment. They used various strategies to reduce leakage, increase drive current, etc. etc. that would allow higher clock rates but the process names were based solely on transistor density.

So if you want a "standardized benchmark" compare them by transistor density. Unless there is someone in this forum who actually makes decisions ordering wafers on a leading edge process, the node names only useful for Intel vs AMD vs Apple fanboying.

TSMC's old vs. new names don't confirm either. TSMC is actually the worst of the two. That is why Intel renamed their nodes.

Having a standard chip available to all foundries for benchmarking purposes, and measuring the physical properties of that chip, would really be a wake up call for a lot of folks.

Rembrandt will definitely be on it's way out, 2023 is competing vs Phoenix.

That being said, Phoenix sticks to the same iGP - next improvement there is with Strix Point in 2024.

A bit concerned for AMD in the mobile space, TBH. They seemingly have nothing to go up against Golden Cove as Rembrandt is "Zen 3+" (unless something is missing from the leaks). I guess we will see how it plays out. All I know is that in another 1-2 generations, many people won't need anything beyond a laptop if this progress keeps up.
 

uzzi38

Platinum Member
Oct 16, 2019
2,703
6,405
146
A bit concerned for AMD in the mobile space, TBH. They seemingly have nothing to go up against Golden Cove as Rembrandt is "Zen 3+" (unless something is missing from the leaks). I guess we will see how it plays out. All I know is that in another 1-2 generations, many people won't need anything beyond a laptop if this progress keeps up.
Nah, RMB will be fine. Sure Alder Lake will have a commanding lead for ST loads, and assuming it has the power it needs it'll beat RMB on MT too, but that's still a big if. We're talking about laptops here after all.

Not to mention the iGPU will be significantly better as well. In the majority of devices where AMD currently finds themselves in now - the more reasonably sized gaming laptops - they'll have their niche where they'll be fine.
 
Reactions: Tlh97

Borealis7

Platinum Member
Oct 19, 2006
2,914
205
106
In the majority of devices where AMD currently finds themselves in now - the more reasonably sized gaming laptops - they'll have their niche where they'll be fine.
i would say those are Consoles, and Intel has 0$ there.
 
Feb 17, 2020
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People should be mindful that whatever marketing person put those slides together got some stuff wrong. Good old marketing.

Anyways, the backside power delivery is by far the most interesting thing from the presentation, so of course nobody's talking about it. Let's walk through it.

1 - There's potential for immediate power savings. CPU's can lose 15% of their voltage due to IR drop. Let's say that backside power delivery cuts it by 1/3 (possible, maybe not likely), that's an immediate 10% power reduction (power scales with the square of voltage, .95^2=.9025).

2 - It gives additional routing resources at the same node. While logic has scaled very well, metal pitch has been moving at a snail's pace. In a node transition where logic density doubles, metal pitch may only scale by 10% on some layers, 5% on others, and not at all on others. As a result, the number of wires available per cell decreases. Ripping out the power grid can free up about 10% of the tracks on most layers and up to 50% on others. Also, it would allow for much less restrictive via placements on lower layers, which could dramatically improve routability.

3 - It trivializes legalization during design. Currently, cells need to be placed around the power grid to avoid low level connections. With backside supply, those connections don't exist, so you can place cells wherever you want. It gives a lot of freedom to standard cell designers to sacrifice metal for improved performance or power of the individual cells, and it gives the chip designers more freedom when optimizing cell placement.

Obviously there are big "If's" and caveats, but this has the potential to improve power efficiency and greatly streamline the design process. Also, most of the metal would be freed up on the highest (aka fastest) metal layers (and it's not even close), so chip architects should be able to increase IPC and reduce power by putting more signals on the fastest layers and reducing their latency.

Meanwhile, we are going to have, on desktop, the biggest IGP gap in history the second RMB shows up.

Yes, because if there's one thing AMD's known for, it's releasing its APU's on desktop platforms in a timely manner.

A bit concerned for AMD in the mobile space, TBH. They seemingly have nothing to go up against Golden Cove as Rembrandt is "Zen 3+" (unless something is missing from the leaks). I guess we will see how it plays out. All I know is that in another 1-2 generations, many people won't need anything beyond a laptop if this progress keeps up.

IMO Golden Cove's not the one to worry about. Sure it'll be faster than Sunny Cove, but also even larger and more power hungry. Gracemont's the one to pay attention to. If Gracemont's good, Alder Lake is good, and the reverse.
 

Hitman928

Diamond Member
Apr 15, 2012
5,657
8,937
136
Yeah I know that, but EUV mainly used for the BEOL? Shouldn't it be used mainly for the smaller constructs in the FEOL?

Gotcha, sorry, the way you put the last part in bold, I thought you were questioning the meaning of BEOL.

I'm not a process expert, but based on my design experience, typically the lithography of the bottom two metal layers (those closes to the silicon) are the ones that need EUV the most. It is hard to meet the metal pitch needs of those layers with all the routing they are responsible for and the minimum width you have to maintain. The FEOL layers don't have this issue since you don't have to route them like you do the metal layers, they are more like the structures that need to be routed between.
 

Gideon

Golden Member
Nov 27, 2007
1,723
3,976
136
Intel renaming their processes like that just seems stupid somehow. Now it's going to be difficult to understand what anyone has been saying about their 10nm and 7nm processes for, I don't know . . . years? Good job sowing confusion Intel.
Yeah, i agree with ... Charlie of all people on this. They should have jumped directly to Angstrom with everything. There have been 130nm processes after all so even 70A would have been totally fine and would have avoided most of the backlash.

It would have been even better to leave 10nm ESF as it is and rename the rest, but there is no need for this temporary "realignment" with samsung and TSMC nodes
 

eek2121

Diamond Member
Aug 2, 2005
3,063
4,299
136
Yeah, i agree with ... Charlie of all people on this. They should have jumped directly to Angstrom with everything. There have been 130nm processes after all so even 70A would have been totally fine and would have avoided most of the backlash.

It would have been even better to leave 10nm ESF as it is and rename the rest, but there is no need for this temporary "realignment" with samsung and TSMC nodes

You have to look at it this way: if Intel knocks it out of the park with ADL, the negative chatter about their fabs should die down.
 

Ajay

Lifer
Jan 8, 2001
16,094
8,106
136
Honestly, I don't care if Intel names their process nodes '10 flying butt monkeys'. If they get competitive again, great!. If they don't, rats! Real competition is the only price control we have. If Intel were to offer 20% more performance/$ the next time I upgrade; I'd consider Intel. Same with AMD (as was the case this time, plus better perf/watt).

Gelsinger hasn't had hardly enough time to make any real changes at Intel. Though, obviously he's applying pressure since he got the process/manufacturing team to commit to this timeline. So while it is to some extent it's a 'dog and pony show', it's also a commitment that the press and investors will hold Intel to. That's not nothing.
 
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DrMrLordX

Lifer
Apr 27, 2000
21,842
11,199
136
You have to look at it this way: if Intel knocks it out of the park with ADL, the negative chatter about their fabs should die down.

Why? The "negative chatter" about their fabs goes far beyond one product or design.

Honestly, I don't care if Intel names their process nodes '10 flying butt monkeys'. If they get competitive again, great!. If they don't, rats!

Except now Intel gets to try to bamboozle investors. Look, we shipped 7nm product in 2021! Yeah, okay.
 

RTX

Member
Nov 5, 2020
90
40
61
14nm -> Intel 14
14nm+ -> Intel 13
14nm++ -> Intel 12
14nm+++ -> Intel 11
...
Before 2018, Skylake was 14nm until they changed it to 14nm+ for Cooperlake's release
You want them to rename their old products to this?
Broadwell 14nm, Skylake 13nm, Kabylake 12nm, Coffeelake 11nm, Cooperlake 10nm
Cannonlake 9nm, Icelake is 8nm, Tigerlake 7nm, Sapphire Rapids 6nm, Raptorlake 5nm?
Meteorlake 4nm, Lunarlake 3nm
 
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