Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

They are not 2 nodes, 10+ is an improvement over 10nm. They normally take a 1 year to mature to get that improvements. If they can't manufacture 10nm now then it is wishful thinking expect Icelake on 10+ in early-mid 2019.

They have given up on Cannonlake/Regular 10 obviously. I think what is being released is just so that they can say they have released something on the node but it won't be of any volume. Now that doesn't mean they won't delay Icelake again if yields don't improve.

 

[Glo.]

By the way, I know distributors and retailers receive the next round of Coffee Lake processors on 2018-02-14, but it seems awfully quiet from lack of pre-release hype from leaks?

And? Where are the parts available?

 

[Bouowmx]

Beats me. Ex: https://www.compsource.com/pn/CM8068403358708/Intel-211/Core-I58600t-Prcsr--Tray-CM8068403358708/

Parts have been listed for at least a week: http://www.shopblt.com/search/s_all=CM80684&s_mfg=INTEL&s_max=100

It's impending, but still, all is quiet.

 

[Glo.]

Beats me. Ex: https://www.compsource.com/pn/CM8068403358708/Intel-211/Core-I58600t-Prcsr--Tray-CM8068403358708/

Parts have been listed for at least a week: http://www.shopblt.com/search/s_all=CM80684&s_mfg=INTEL&s_max=100

It's impending, but still, all is quiet.

Anything else they should receive today? New Chipsets, SSDs(660p)?

 

[IntelUser2000]

Anything else they should receive today? New Chipsets, SSDs(660p)?

Chipsets don't seem to be listed but newer Optane drives(800P/M10) are listed. They were all listed Feb 14 but none are here.

On February 26, there's a presentation by Rob Crooke, the SVP and GM of NVM group at Intel at Morgan Stanley Tech, Media & Telecom conference. Perhaps the release will be there? Including the chipsets and chips.

The Coffeelake-S release seems to be more towards end of Q1 if we look at the presentations on the previous page about Cascade Lake.

VNNI support？？ fake

Fake? Everything points towards being an Intel slide. In fact there have been more accurate ones than actual fake ones. They can always update the ISA guide to include Cascade Lake for VNNI. Sometimes they do that intentionally, likely to prevent leaks to the public.

 

[csbin]

Fake? Everything points towards being an Intel slide. In fact there have been more accurate ones than actual fake ones. They can always update the ISA guide to include Cascade Lake for VNNI. Sometimes they do that intentionally, likely to prevent leaks to the public.

Ice Lake and later

So Skylake Xeon D？

 

[csbin]

Sometimes they do that intentionally, likely to prevent leaks to the public.

prevent leaks？

Cascade Lake in 2018
Ice Lake in 2019

 

[mikk]

Looks completely legit, nobody is going to fake these slides. Fakes are extremely rare on Intels side and to fake something like VNNI is boring, you would expect a faker would fake more exciting stuff than this. Basically every leak is answered with "fake" and almost every time it was legit.

 

[Arachnotronic]

8130U is most likely QC Kaby Lake Refresh with two of the cores disabled and probably 2 MB cut.

The 8121U is the only one that's Cannon Lake although it does confirm they are intending to release a 2+2 part at some point.

Why would they sell a quad core KBL-R with two cores disabled? A Kaby Lake Refresh with only two cores is called a Kaby Lake.

 

[Arachnotronic]

Ice Lake and later

So Skylake Xeon D？

Why would someone fake these roadmaps? A lot of work for what?

 

[csbin]

Why would someone fake these roadmaps? A lot of work for what?

true roadmaps？



ok，Skylake Xeon-D in 2019 q2-2020？

 

[dooon]

Fake or True ?
Intel "IOTG (Internet of Things Group)" Roadmap.

thx Google.
CCL

 

[IntelUser2000]

Why would they sell a quad core KBL-R with two cores disabled? A Kaby Lake Refresh with only two cores is called a Kaby Lake.

No, KBL-R includes additions to the die that KBL doesn't. For example the ISP.

Core disabling is done for yield purposes. You know this.

 

[Arachnotronic]

No, KBL-R includes additions to the die that KBL doesn't. For example the ISP.

Core disabling is done for yield purposes. You know this.

Negative. The ISP has been unchanged since the introduction of Skylake-U. It is the H/S CPUs that lack this, which is why WikiChip made a point of highlighting it — to show that Intel made a new U die instead of repurposing an H die.

 

[firewolfsm]

Negative. The ISP has been unchanged since the introduction of Skylake-U. It is the H/S CPUs that lack this, which is why WikiChip made a point of highlighting it — to show that Intel made a new U die instead of repurposing an H die.

No there were changes to Kabylake that made video decoding more energy efficient. Also Kabylake-R has updated video output (HDMI 2.2 iirc). Since the i3 KL-R has this as well it's probably a salvaged die.

 

[jpiniero]

Why would they sell a quad core KBL-R with two cores disabled? A Kaby Lake Refresh with only two cores is called a Kaby Lake.

I thought they might use the Kaby Refresh die because of the improved ISP, and to yes salvage quad core dies. But according to Ark they are indeed using a dual core Kaby Lake die.

 

[IntelUser2000]

Negative. The ISP has been unchanged since the introduction of Skylake-U. It is the H/S CPUs that lack this, which is why WikiChip made a point of highlighting it — to show that Intel made a new U die instead of repurposing an H die.

Why do you think they are the same?

There are:
-Skylake H/S(4 cores)
-Skylake U with ISP(2 cores)
-Kabylake U with ISP(2 cores)
-Kabylake Refresh with ISP(4 cores)
-Kabylake H/S(4 cores)

There is no other -U chip with 4 cores and ISP than KBL-R. They would have had to make a new die because it adds 2 cores from what dual core Kabylake had.

 

[PeterScott]

I thought they might use the Kaby Refresh die because of the improved ISP, and to yes salvage quad core dies. But according to Ark they are indeed using a dual core Kaby Lake die.

I don't remember Intel ever using die scavenging/disabling on low core count parts.

All Intel dual cores have been native dual core dies.

 

[Arachnotronic]

I thought they might use the Kaby Refresh die because of the improved ISP, and to yes salvage quad core dies. But according to Ark they are indeed using a dual core Kaby Lake die.

There is no improved ISP in Kaby Lake refresh, it's the same one as in the Skylake-U die. The only IP that saw an update was the media engine, which was updated with Kaby Lake and retained with Kaby Lake Refresh and Coffee Lake.

 

[jpiniero]

http://ranker.sisoftware.net/show_s...bc81a7cef3d5bd80a6dee3c5a0c5f8c8ee9da098&l=en

Icelake U/Y GPU spotted again. Looks like GT2 has 48 EUs (up from 40 on Cannon Lake, if it actually appears)

 

[mikk]

Only if this is a fully enabled GT2. It would mean there are 6 subslices for GT2 Gen11. The ICL patchwork did mention there are 8 subslices.

 

[IntelUser2000]

Only if this is a fully enabled GT2. It would mean there are 6 subslices for GT2 Gen11. The ICL patchwork did mention there are 8 subslices.

There's another possibility. Now there are 6 EUs per subslice. 6EUs x 8 subslices = 48EUs.

The reason would be to increase sampler throughput and reduce load on the L1/L2 caches.

Interesting Sisoftware reports it as Gen 11 LP. The LP designation has been bound to Apollo Lake for Gen 9 and earlier. The clock speed at 600MHz may be legitimate then. The Gen 9 LP on Pentium Silver J5005 is clocked at 800MHz.

Gen 11 LP may have been a better fit with Core M parts than regular Gen 11.

 

[IntelUser2000]

So the reason Skylake-X and SP cores are so large isn't just because of 1MB L2 and AVX-512. AVX-512 in terms of added area is actually relatively small.

There's also the CHA(Caching Home Agent), Snoop Filter, power management, and logic needed for the mesh. I would say about half of the new space is taken up by them. In Broadwell EP chips, the CHA and Snoop filter functions were spread elsewhere, so the cores looked similar in size to consumer Broadwell ones. With Skylake, each cores have CHA and Snoop Filters.

They are actually critical for server chips. But they aren't necessary for HEDT. The HEDT market is way too small to justify a dedicated core development though.

 

[mikk]

There's another possibility. Now there are 6 EUs per subslice. 6EUs x 8 subslices = 48EUs.

This is another possibility. Another possibility is that Gen11 LP differs from Gen11 regular in EU count, like Gen9 LP (max 18 EUs) to Gen9 regular (24 EUs). 48 EUs is on the low side for mid 2019-2020 because it's only a doubling from 2015. But at least they are moving forward with their refresh gens on 10nm, so it's not a stagnation unlike all the boring 14nm refresh gens later on.

Interesting Sisoftware reports it as Gen 11 LP. The LP designation has been bound to Apollo Lake for Gen 9 and earlier. The clock speed at 600MHz may be legitimate then. The Gen 9 LP on Pentium Silver J5005 is clocked at 800MHz.

As usual I wouldn't read too much into clock speeds on such early ES sample leaks. I doubt this is somehow representative for SKUs available in over a year.

 

[ksec]

Slightly Off Topic, Am i the only one thinking the whole Intel is very very messy?

We have Skylake ,KabyLake, CoffeeLake, and coming Cannonlake all over the place, then Icelake coming in possibly 2019?

Then there is Cannonlake 2 + 0, I am assuming this is a CPU only instead of having GPU silicon disabled. How is it for ?