In this case, Intel themselves decided to try and jump over a 40 m tall fence while carrying a backpack that weighs 5 tons. Every time they tried to jump and fell back after 3 cm, they kept reassuring everyone that everything is fine, we're currently flying, totally mid-air and we'll arrive on the other side at the planned date. Then a year after the planned date, they took a polaroid picture of themselves, named it cannon lake and threw it over the fence.There's never been a time where the whole industry hit a wall, so I see no reason to expect that in the future. If one company hits a wall their chances of recovery and catching up become more dim with each cycle because missing out on that juicy early depreciation really hits the bottom line. I expect either Intel or Samsung to fall out of the race before the end of the decade, then we'll see what happens when it is down to just two.
Aha! So that's why they called it Cannon Lake!In this case, Intel themselves decided to try and jump over a 40 m tall fence while carrying a backpack that weighs 5 tons. Every time they tried to jump and fell back after 3 cm, they kept reassuring everyone that everything is fine, we're currently flying, totally mid-air and we'll arrive on the other side at the planned date. Then a year after the planned date, they took a polaroid picture of themselves, named it cannon lake and threw it over the fence.
At that time, few could have predicted that AMD was doing the right thing. Funnily, it took Intel's bungling of their process leadership to prove that AMD went in the right direction. It would be a very different world today if Intel had stayed on course and Alder Lake were on 7nm.
There's never been a time where the whole industry hit a wall, so I see no reason to expect that in the future. If one company hits a wall their chances of recovery and catching up become more dim with each cycle because missing out on that juicy early depreciation really hits the bottom line. I expect either Intel or Samsung to fall out of the race before the end of the decade, then we'll see what happens when it is down to just two.
GlobalFoundries is down, but not out. They've recently gone public and have been raising a ton of cash. They are also onboarding new customers. While unlikely in the near term, I can see them potentially making a play in the future. Well, rather, I wouldn't count them OUT from making a play in the future.Yes, TSMC can. But that just reinforces the smaller and smaller group of cutting edge companies. The real question is can anyone not named in your post do so?
If Intel had not been stuck on 14nm for all those years, things would have been very different. If 1st gen Ryzen had to compete with an Intel 10nm or (especially) 7nm part, AMD likely would have never been able to get a foothold. They would have imploded. Intel's multiple slip ups were key to AMD coming back.The first time I read about a fabrication plant was when it used to cost $1 or $2 billion and AMD had gone fabless and everyone said their days were numbered. At that time, few could have predicted that AMD was doing the right thing. Funnily, it took Intel's bungling of their process leadership to prove that AMD went in the right direction. It would be a very different world today if Intel had stayed on course and Alder Lake were on 7nm.
I'm not sure I'd classify Gelsinger's actions as panicked. It just might seem that way because we're unused to Intel having a competent CEO. Clearly Intel doesn't -need- the money in order to execute their plans seeing as how they still make more than TSMC. But why spend the company's money if the political environment means you can spend government money instead? Exact same approach that TSMC and Samsung take, we just normally don't hear as much about it because it's mostly been in their respective home countries.
I remain somewhat surprised that Samsung is continuing to pour money into their foundry ambitions. Checking their Q3 2021 earnings, the Semiconductor segment looks good at first glance with $22.3B in revenue... but $17.6B of that is on their memory side leaving 'only' $4.7B for foundry and LSI. Clearly it's still a fair amount of revenue, but still less than 1/3 of TSMC and Intel. My impression here has always been than Samsung is shifting investment to the foundry side to try and avoid the 'feast or famine' cycles of the memory business.
Individual process nodes aside there are physical limits to how small things can get. Some of that is a tricky engineering problem, but after that is hard reality. It won't be a matter of scaling down when there's no down left.
Getting past that is going to take a lot of work using other materials or looking to gain performance in other ways beyond simply shrinking the transistors. That's probably going to require a lot of investment that won't work out or won't produce useful results.
Individual process nodes aside there are physical limits to how small things can get. Some of that is a tricky engineering problem, but after that is hard reality. It won't be a matter of scaling down when there's no down left.
TSMC's CEO believes we have at least 20 years to run before we reach those limits. Everyone who has claimed that physical limitations are coming around the corner soon has been proven wrong.
As an overall size I think they stopped at the 10-20nm range. You can argue until your face is blue and some parts are smaller than the others but pretty much it has stopped. This is roughly similar to NAND using larger transistors but stacking them instead.
Is it possible to combine DUV and EUV, taking advantage of the benefits of each in a single die?That is cause of limits of litho. Despite being touted as savior of industry for a decade, EUV in its 0.33NA form does not really allow tigher features than good old 1+ NA DUV with multi patterning. Despite 193nm vs 13.5nm wavelengths, NA plays huge role.
So EUV has economical advantages of less masks, better yields and so on, but the features printed are not that smaller than what is possible with DUV. So when faced with already "tight" structure like SRAM, the scaling is barely 0.8 or so lately between TSMC 7nm and 5nm processes, cause DUV was like 40nm MMP and EUV limit according to https://semiengineering.com/gearing-up-for-high-na-euv/ is ~30nm. And after Intel debacle with pushing things too far, probably noone dares to bet the farm on testing exact limit in high volume, so it is probably 36nm in practice.
The only ways to move to smaller features are: multi patterned 0.33NA EUV or moving to high NA of 0.55 EUV. Both have their own challenges that were highlighted in article above.
Is it possible to combine DUV and EUV, taking advantage of the benefits of each in a single die?
Not really. Line edge roughness and dimensional consistency under DUV was going down the crapper. It took massive investments by R&D by Fabs and equipment OEMs to get those to an acceptable range. Electrostatic variation in xtors over a 1000 sq. microns was at the limit. EUV was really needed at 14nm, but was running late.It's already done, mixing the two, using EUV to reduce the mask numbers that would be required by use of DUV multi patterning + obviuosly DUV is used in upper layers where pitches are in hundreds of nm. The key factor is that despite apparent massive difference in wavelength 13.5nm vs 193nm, DUV was pushed so far with multi patterning and high NA techniques that features printed are very similar. ~40nm for SADP and 30-32nm according to that article for EUV 0.33NA systems. If we take into account SAQP with 36nm or so and take a safe pitch for EUV - they are interchangaable if ignoring economic factors.
Correct. For example Intel's Meteor Lake will use EUV mostly for the back end of line (BEOL) portion of the chip. Intel doesn't have enough EUV machines to make the whole chip with EUV.It's already done, mixing the two, using EUV to reduce the mask numbers that would be required by use of DUV multi patterning + obviuosly DUV is used in upper layers where pitches are in hundreds of nm.
There's still 20 years left before physical limits prevent going any further??It's going to take even higher NAs, more masks an exotic materials to keep pushing EUV over the next 20 years.
I'm not sure I'd classify Gelsinger's actions as panicked. It just might seem that way because we're unused to Intel having a competent CEO. Clearly Intel doesn't -need- the money in order to execute their plans seeing as how they still make more than TSMC. But why spend the company's money if the political environment means you can spend government money instead? Exact same approach that TSMC and Samsung take, we just normally don't hear as much about it because it's mostly been in their respective home countries.
I remain somewhat surprised that Samsung is continuing to pour money into their foundry ambitions. Checking their Q3 2021 earnings, the Semiconductor segment looks good at first glance with $22.3B in revenue... but $17.6B of that is on their memory side leaving 'only' $4.7B for foundry and LSI. Clearly it's still a fair amount of revenue, but still less than 1/3 of TSMC and Intel. My impression here has always been than Samsung is shifting investment to the foundry side to try and avoid the 'feast or famine' cycles of the memory business.
Intel must have promised to make him a billionaire or something. Or he just loves Intel like he's said a few times in interviews.I agree with much of this. But Gelsinger has 5 years to turn around Intel or it will be too late (plus the board will enforce the retirement requirement on him). So he is out there trying to get any favorable advantage he can before it’s game over. He has become the biggest PR man and lobbyist in the industry. He bashes TSMC while working with them at the same time. He's arguing against government subsidies for US based TSMC Fabs, even though it’s in the government’s interest to hedge their bets. Maybe he is not 'panicked', but there sure is a fire under his butt.
Not really. Line edge roughness and dimensional consistency under DUV was going down the crapper. It took massive investments by R&D by Fabs and equipment OEMs to get those to an acceptable range. Electrostatic variation in xtors over a 1000 sq. microns was at the limit. EUV was really needed at 14nm, but was running late.
Wow, color me perplexed! I would have thought EUV on FEOL would be far more important. So, it must really be about mask sets more than anything else right now.Correct. For example Intel's Meteor Lake will use EUV mostly for the back end of line (BEOL) portion of the chip. Intel doesn't have enough EUV machines to make the whole chip with EUV.
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Yes, he surely does, that I am totally convinced of. Look at his personal history - he is pretty much the human incarnation of the company.Intel must have promised to make him a billionaire or something. Or he just loves Intel like he's said a few times in interviews.
A cool $100M in restricted stock just for starters. In addition to a net worth already in the 8 figure range: https://www.oregonlive.com/silicon-...ger-with-a-package-valued-at-116-million.htmlWow, color me perplexed! I would have thought EUV on FEOL would be far more important. So, it must really be about mask sets more than anything else right now.
That said, I don't see how Fabs will be able to push GAA without EUV; which could just be my lack of understanding and imagination.
I'm just parroting what Ian Cutress posted here under "2022 H2, Intel 4": https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foverosWow, color me perplexed! I would have thought EUV on FEOL would be far more important. So, it must really be about mask sets more than anything else right now.
That said, I don't see how Fabs will be able to push GAA without EUV; which could just be my lack of understanding and imagination.
Intel's reasoning is beyond my CPU knowledge. I suspect it is because the FEOL is still relatively large components in Intel 4. It isn't until Intel 3 where these are made high density.Intel earlier this year stated that its Meteor Lake processor will use a compute tile based on this process node technology, and the silicon is now back in the lab being tested. Intel expects a 20% performance per watt gain over the previous generation, and the technology uses more EUV, mostly in the BEOL.
That is cause of limits of litho. Despite being touted as savior of industry for a decade, EUV in its 0.33NA form does not really allow tigher features than good old 1+ NA DUV with multi patterning. Despite 193nm vs 13.5nm wavelengths, NA plays huge role.
So EUV has economical advantages of less masks, better yields and so on, but the features printed are not that smaller than what is possible with DUV. So when faced with already "tight" structure like SRAM, the scaling is barely 0.8 or so lately between TSMC 7nm and 5nm processes, cause DUV was like 40nm MMP and EUV limit according to https://semiengineering.com/gearing-up-for-high-na-euv/ is ~30nm. And after Intel debacle with pushing things too far, probably noone dares to bet the farm on testing exact limit in high volume, so it is probably 36nm in practice.
The only ways to move to smaller features are: multi patterned 0.33NA EUV or moving to high NA of 0.55 EUV. Both have their own challenges that were highlighted in article above.
Unfortunately it is a distinct possibility that Gelsinger will only have 5 years as CEO. I sure wouldn't bet on it though since it's an arbitrary board decision and the only potential historical application of it would have been with Craig Barret who transitioned from CEO to chairman of the board at age 65. While perhaps not quite on the same level as those that preceded him, I'd say Craig Barret was still a solid Intel CEO. Far better than the trio that followed that ran Intel like any generic big business.I agree with much of this. But Gelsinger has 5 years to turn around Intel or it will be too late (plus the board will enforce the retirement requirement on him). So he is out there trying to get any favorable advantage he can before it’s game over. He has become the biggest PR man and lobbyist in the industry. He bashes TSMC while working with them at the same time. He's arguing against government subsidies for US based TSMC Fabs, even though it’s in the government’s interest to hedge their bets. Maybe he is not 'panicked', but there sure is a fire under his butt. It’s not his fault that Intel is in the predicament that they are. It's the BODs over the last ~20 years, who choose profits and vertical growth over excellence in their core business and appointed CEOs that would accomplish those goals.
The last CEO, who really understood what Intels was, what it’s strengths were and how those strengths needed to be upheld and advanced was Andy Grove.