Discussion Intel current and future Lakes & Rapids thread

[itsmydamnation]

Its funny (sad way) watching Exist50 argue semantics time and time again picking a few line out of many many posts which when viewed holistically paint a very consistent picture .

I think if we are being honest here we should be picking the clock rate that is the knee of the curve for each processor, that shows its target range...

But then that wouldn't go well for Exist50 would it?

 

[Exist50]

More than drastic actually..

At 3.7GHz voltage/frequency are still in a square law curve power wise, but the higher the frequency the more it morph into a cubic and even quadratic curve, wich is the case of ADL since the last drop of frequency is squeezed out of the P cores, so overvoltage of E cores is huge when the chip run at full tilt.

That happens at different points for different cores. You can see some VF curves in this video around 17:53.

Little bit skeptical of the piecewise Atom VF curve, but you can see that iso-voltage, Golden Cove always clocks higher. The greatest inefficiency comes at voltage >1.2V, where Gracemont stops scaling.

 

[Exist50]

Its funny (sad way) watching Exist50 argue semantics time and time again picking a few line out of many many posts which when viewed holistically paint a very consistent picture .

I think if we are being honest here we should be picking the clock rate that is the knee of the curve for each processor, that shows its target range...

But then that wouldn't go well for Exist50 would it?

Lmao, it's "semantics" when I'm right, and a "very consistent picture" when someone doubles down on being provably wrong? I guess this is what I get for feeding the trolls, hah.

 

[dmens]

Since you don't appear to remember your own words:


So, again, if 3.3GHz the max, as you claimed explicitly, then how is 4+GHz possible?

Because Alderlake atoms have a higher acceptable wattage/thermal limit than Tremont, that's how. Christ, how thick are you?

Why are you still grasping at straws on this? You already demonstrated you are utterly clueless on what silicon design targets are, and conflated that with maximum achievable frequency. Just give up already. Go ask your friends for more leak scraps so they can laugh at you more.

And, again, why did you claim that the accurate leak of the 12900k's clocks was laughable?

It is laughable because I underestimated how desperate Intel is to get a benchmark win. I know this is what gets fanboys wet but from an engineering point of view, 10 watt atoms cores are kinda sad.

Uh, they did have specific points labeled, and since my extrapolation was correct while yours was almost a GHz off, it's hilarious that you're still doubling down. But at least you're now indirectl acknowledging that 3.9+GHz is possible, so that's some progress.

And oh yeah, how are we discussing this at all when you claimed Alder Lake shouldn't even be out?

They are no labels. Labeled VF curves are never released to be public. You will never prove your BS on four different designs on two different frequency ranges and two different processes. All I need to prove you wrong is 10 watt Gracemont vs 2.5 watt Tremont.

 

[dmens]

Its funny (sad way) watching Exist50 argue semantics time and time again picking a few line out of many many posts which when viewed holistically paint a very consistent picture .

I think if we are being honest here we should be picking the clock rate that is the knee of the curve for each processor, that shows its target range...

But then that wouldn't go well for Exist50 would it?

LOL. It is not even semantics, it is just basic engineering terminology and knowledge. Look at what just happened. You say "design to x ghz" to any engineer in the business, they will instantly know what that means. Then we can have a meaningful conversation about simulation corners.

But with this guy, you get "BUT YOU SAID IT CAN NEVER GET TO 4GHZ EVVARRRRRRRR!!!!!!"

My mistake is assuming people talk the talk since I have been doing this for so long. My bad.

 

[DrMrLordX]

And yet, in order to get Gracemont clocks to 3.9ghz, it required a massive voltage boost, well over what Intel would maximally put into Tremont.

To be fair, Alder Lake's power management is kinda goofy. The Gracemont clusters get excess voltage if the Golden Cove cluster goes beyond 4.7 GHz, and that's in all-core workloads, not to speak of what happens when the Gracemont cluster is partially or fully-loaded while only one of the Golden Cove cores tries boosting to 5.1 GHz or so. Intel really needed separate power planes for the different clusters.

 

[itsmydamnation]

Lmao, it's "semantics" when I'm right, and a "very consistent picture" when someone doubles down on being provably wrong? I guess this is what I get for feeding the trolls, hah.

You know the knee of the curve in the video you posted for the E core was 3ghz right?

 

[IntelUser2000]

What "outsize capabilities"? When has there been an Atom that didn't suck? Did I miss when real products people wanted actually shipped with that POS?

Just because the absolute performance is low doesn't mean the engineering of that said product is poor, which is your argument.

Bay Trail actually was a competitive core and proved x86 Tablets don't have be thick, heavy devices sporting a fan with 5 hours of battery life. I know, because I had one. The Venue Pro I had got 7 hours of battery life with a 18WHr pack!

Airmont was ignored because of the lack of improvements on the performance area but the area reduction with a single process generation being 1/3rd of the Silvermont core showed it's potential. Because it was totally ARM levels of perf/mm2.

Gracemont is a Skylake-class core at fraction of the size. At the level of their progress it's about a generation away before their brand-spanking new Core(Golden Cove) is outclassed by it.

You could say that Gracemont isn't special and the Core team has been sucking but either way his point saying "outsized capabilities" is correct. Everyone has been drooling at 5GHz Skylake while sneakily and steadily the "Atom" has been nipping at it's heels!

 

[Exist50]

You know the knee of the curve in the video you posted for the E core was 3ghz right?

Unfortunately, the claim was explicitly about max/boost clock speed, as you could see by clicking on any of the comments I quoted. It's a desperate lie to hide how laughably wrong he was.

 

[IntelUser2000]

If you think about the saddest thing about the contra-revenue nonsense was that it caused Intel to abandon the Tablet market entirely, when they could have just continued to develop on the Tablet efforts slow and steady. They had a usable product which would have worked fine at least for Windows.

But nooo, they said "we need massive marketshare at all costs". Who cares about execution when you can basically bribe people?

Everyone said they couldn't and when they actually pulled something that had the slightest bit of chance to turn things around they made decisions to kill it. It's like they eventually believed the naysayers.

Little realized fact is Intel's 90% server share didn't happen overnight. They got it through a decade of execution. Back in the early Core era they were under 50% in server marketshare. Intel didn't pay the vendors to use them, excellent products like Core and Nehalem caused their marketshare to grow.

A proper Goldmont/Goldmont+/Tremont Tablets would have sold, and I'm not talking about vendors shoehorning them inside "Tablets", because after Airmont they gave up on the Tablet platform entirely. All the work they made regarding size and power use was thrown away.

 

[dmens]

Unfortunately, the claim was explicitly about max/boost clock speed, as you could see by clicking on any of the comments I quoted. It's a desperate lie to hide how laughably wrong he was.

This is just pitiful now.

Here is yet another engineering revelation for you: a typical simulation point is at the voltage point or slightly past the point where gains flatten (i.e. where that bend is). It is usually the highest voltage simulated. Hence, "designed to x ghz" (at that voltage, as in the design should be converged at those points). Again, whatever crazy voltage is required for max boost is not simulated at all for reasons I already stated, and you failed to understand.

@itsmydamnation got it right, and you are wrong, yet again.

 

[Exist50]

This is just pitiful now.

Here is yet another engineering revelation for you: a typical simulation point is at the voltage point or slightly past the point where gains flatten (i.e. where that bend is). It is usually the highest voltage simulated. Hence, "designed to x ghz" (at that voltage, as in the design should be converged at those points). Again, whatever crazy voltage is required for max boost is not simulated at all for reasons I already stated, and you failed to understand.

@itsmydamnation got it right, and you are wrong, yet again.

You do realize that people can see your post history, right?

 

[dmens]

You do realize that people can see your post history, right?

LOL. Look in the mirror. Go ask your leaker friends about what design landing zones are, maybe one of them is an actual engineer and not a PowerPoint jockey and might be nice enough to explain it until you maybe get it through your thick skull. Maybe.

 

[Exist50]

LOL. Look in the mirror. Go ask your leaker friends about what design landing zones are, maybe one of them is an actual engineer and not a PowerPoint jockey and might be nice enough to explain it until you maybe get it through your thick skull. Maybe.

Again, people can see your post history, including what I quoted. Throwing a fit won't change that.

 

[dmens]

Again, people can see your post history, including what I quoted. Throwing a fit won't change that.

Awwwww how cute, you're trying to be condescending. That doesn't really work if you don't have a clue what you are talking about.

 

[coercitiv]

The greatest inefficiency comes at voltage >1.2V, where Gracemont stops scaling.

It doesn't stop scaling (yet). The V/f curves presented in that video are those embedded in the silicon, and they extracted that information by manually changing the frequency of the cores under special conditions in order to isolate values for each frequency. The good thing about this method is we get values determined by the manufacturer (with some influence from the board itself, although SkatterBencher did his best to isolate that), the bad thing is we only get values for the programmed max clocks on the SKU. In the case of the 12700K that means 38x for E-cores, 50x for P-cores, 46x for the bus.

When it comes to the E-core, the main takeaway from the graph is the core scales well power wise until 3Ghz. After that inflection point it moves to a different voltage slope which will eventually turn problematic, but not until it reaches 4.1Ghz - 4.2Ghz.

To conclude: over-voltage on the E-cores is a problem only at 200W+, where overall efficiency is lying in a pool of blood anyway. At 150W TDP the E-cores get just an 50mV over-volt (based on observation), and this would probably get nullified at 125W. There is no massive inefficiency introduced by the single voltage rail on the desktop, and I expect ADL-P to have a different topology for power delivery.

 

[JoeRambo]

At 150W TDP the E-cores get just an 50mV over-volt (based on observation), and this would probably get nullified at 125W. There is no massive inefficiency introduced by the single voltage rail on the desktop, and I expect ADL-P to have a different topology for power delivery.

Wrong. Anyone with ADL can test it for themselves. With 1P+8E enabled and fixing Ring/1-P Core @33 and running 8 threads of Linpack with task affinity on E-Cores:

3.3Ghz @ 0.95V 29W total package power
3.3Ghz @ 1.05V 36W total package power
3.3Ghz @ 1.15V 47W total package power
3.3Ghz @ 1.25V 58W total package power
3.3Ghz @ 1.35V 71W total package power

4.0Ghz @ 1.25V 67W total package power
4.0Ghz @ 1.35V 82W total package power

Perf is 110Glops @ 3.3Ghz and 133Gflops @ 4Ghz

0.95V @ 3.3Ghz and with 1 E-core running Linpack package power is 9W
1.25V @ 4 ghz and with 1 E-core running Linpack package power is 20W

So you can already see the damage inflicted by corporate marketing morons on E-Cores. The chip is incredibly efficient ~1.05V and that is where FIVR is feeding L2 core cluster voltage and was probably meant to feed E-Cores as well, yet marketing asked for more clocks and that required power beyond what FIVR was capable of supplying.
Once on common rail for voltage things are completely downhill and wastes at least 100% where E-Cores are incredibly efficient and trades 20% extra performance for 200-250% more power consumption when "unleashed".

EDIT: to put things into perspective 8C ADL @5Ghz is 560GFlops of Linpack, E-Cores are not really adding much in FP/FMA heavy tasks, yet they add ~33% CB23 score to the total.

 

[coercitiv]

Wrong.

Not wrong at all. Anyone with ADL can test it for themselves. With stock config and limiting power to 125W or 150W you will see the P cores and E cores will clock in such a way relative to each other that the E cores will barely be over-volted considering their operating frequency.

Notice how E-core @ 3.8Ghz requires roughly the same voltage as P-core at 4.7GHz. Based on this we can conclude P-core voltage isn't introducing large inefficiencies for E-cores in MT workloads as long as power limits aren't high enough to allow P-core clocks higher than 4700Mhz. For example running CB23 on 12700K with PL1 = PL2 = 150W results in 4.5Ghz on P-cores and 3.5Ghz on E-cores. That's ~1.15V versus ~1.1V.

Surprise surprise, when operating with sane power limits such as 125-150W the E-cores end up clocking bellow 3.5Ghz, and that's with just 1 cluster available on the 12700k. It's almost as if Intel engineers knew how to tune this CPU for proper 125W TDP operation instead of the ridiculous 240W enforced by marketing. I'm not a E-core fan at all, in fact I've always criticized Intel's decision to introduce them so early on the desktop, but engineering wise the decision to go with a single voltage rail would have worked perfectly fine as long as stock power was kept within it's intended dynamic range.

I do agree with on this though: marketing / higher execs screwed up ADL-S. The 12900K and 12700K in their stock config are NOT what engineers had in mind when they designed the chip.

 

[JoeRambo]

Not wrong at all.

The 12900K and 12700K in their stock config are NOT what engineers had in mind when they designed the chip.

Both can't be true at same time tho

We have two extreme points:

1) Full on Linpack showing horrible wastage
2) Some magic arbitrary point on TDP line, where P-Cores pushed down in clocks to require low voltage for E-Cores to be efficient* ( * as in +500mhz beyond what is really efficient here ).

Some obvious fact arise from these two points: if we move TDP and/or load from that arbitrary point, efficiency goes down.

Full core load decreases to allow more P-Core clocks? More watts wasted.
Load is not saturating CPU, say 8P C + 4E C loaded but far below from TDP? More watts wasted.
Increase TDP to allow more performance? More watts wasted.

 

[coercitiv]

2) Some magic arbitrary point on TDP line, where P-Cores pushed down in clocks to require low voltage for E-Cores to be efficient* ( * as in +500mhz beyond what is really efficient here ).

Some obvious fact arise from these two points: if we move TDP and/or load from that arbitrary point, efficiency goes down.

Let's add another point on the TDP line, see how the chip behaves.

Here's CB23 on 12700K with TDP limited to 65W.

Spoiler: CB23 clocks

P-cores run at 3.2GHz, E-cores are at 2.7Ghz. According to the SkaterBencher V/f curve, the factory voltage for E @ 2.7Ghz is roughly the same as the one for P @ 3.2Ghz (around 0.89V). In fact, in this case the Vcore is dictated by the Ring voltage request, which at 3.2Ghz ends up being higher than both P-core and E-core VIDs.

So we have a slight delta in voltage at 150W and no problem with voltage delta at 125W and 65W. Are you still sure this is just a case of "magic arbitrary" TDP point?

 

[LightningZ71]

I'm still not 100% on board with the power usage criticism for the "K" parts. Isn't the whoe point of the "k" parts to be performance at all costs? Isn't there an entire line of non-k parts that has sane power budgets? Don't they also have a "t" line for efficiency optimized parts with even tighter power limits?

I personally don't care about the power usage for the K parts. They are advertised as unlocked parts for overclocking and seem to fit that role well.

 

[JoeRambo]

So we have a slight delta in voltage at 150W and no problem with voltage delta at 125W and 65W. Are you still sure this is just a case of "magic arbitrary" TDP point?

I don't think adding 65 or 10W TDP proves anything beyond what was proven already with 1XX watts of TDP, where P-Cores are no longer dominating VID requests?

How about we get back to same 1XX watts, but instead of running 20 threads of CB, run 18? 15? 12?
Now those are the points where efficiency comes into play again.

 

[mikk]

Let's add another point on the TDP line, see how the chip behaves.

Here's CB23 on 12700K with TDP limited to 65W.

Spoiler: CB23 clocks

View attachment 55312

P-cores run at 3.2GHz, E-cores are at 2.7Ghz. According to the SkaterBencher V/f curve, the factory voltage for E @ 2.7Ghz is roughly the same as the one for P @ 3.2Ghz (around 0.89V). In fact, in this case the Vcore is dictated by the Ring voltage request, which at 3.2Ghz ends up being higher than both P-core and E-core VIDs.

So we have a slight delta in voltage at 150W and no problem with voltage delta at 125W and 65W. Are you still sure this is just a case of "magic arbitrary" TDP point?

0.93V for 2700 Mhz is quite poor actually. My i7-1165G7 is running at 0.82V for 2800 Mhz on default under full AVX MT load. In a mobile ULV SKU at 2700 Mhz the Vcore shouldn't exceed 0.8V.

 

[IntelUser2000]

P-cores run at 3.2GHz, E-cores are at 2.7Ghz. According to the SkaterBencher V/f curve, the factory voltage for E @ 2.7Ghz is roughly the same as the one for P @ 3.2Ghz (around 0.89V). In fact, in this case the Vcore is dictated by the Ring voltage request, which at 3.2Ghz ends up being higher than both P-core and E-core VIDs.

0.93V for 2700 Mhz is quite poor actually. My i7-1165G7 is running at 0.82V for 2800 Mhz on default under full AVX MT load. In a mobile ULV SKU at 2700 Mhz the Vcore shouldn't exceed 0.8V.

The mobile chips are also optimized for different curve than the desktop. The mobile ones will struggle to reach the frequency levels of the desktop chips at the same voltage level.

So there's the possibility that the "inefficiency" of Gracemont with Alderlake-S is reversed with Alderlake-P.

 

[IntelUser2000]

Sapphire Rapids might end up being 80-100% faster than the predecessor Icelake-SP. ICL has issues clocking high and it regressed noticeably compared to Cascade Lake. SPR will fix this plus clock higher than Cascade Lake.

20% uarch gains, 40% more cores, 10-15% higher clocks is going to be a substantial gain.

It's interesting how if you look from that perspective, it only takes a year before the competitive landscape changes. If they got this last year Intel would have had a competitive Xeon as the above should result in beating Milan by a bit in quite a few applications.

It'll be quite a contest in consumer desktop. Raptorlake versus Zen 4. 8 additional E cores should result in 20% gain, with faster P cores resulting in an overall 25% gain in MT. Golden Cove is what, ~10% faster than Zen 3 at equal clocks? Zen 4 might be faster per clock by a bit but Intel clocks higher so that cancels out.

V-Cache and HBM is going to be a situational thing. Neither will be widely available nor implemented across the board.