That's why you have some P cores as well. Workstation tasks are a mix of single, lightly, and highly threaded. Hybrid can cover the gamut.
Yes, but due to lack of Competition and other factors(like prioritizing higher margin products like EPYC) AMD HEDT has fallen back almost an entire generation(For AMD, but a full generation for Intel)Let me put it this way, Threadripper is more or less the ideal product.
Sure, but that relationship not only does exist, but is fundamental to the value proposition E cores offer in the first place.Yeah, I don't doubt that. That conclusion is more a consequence of how large the P cores are and/or how small the E cores are. If that relationship didn't exist, it would be more feasible to do a configuration where you have more P cores than E cores.
Yes, but due to lack of Competition and other factors(like prioritizing higher margin products like EPYC) AMD HEDT has fallen back almost an entire generation(For AMD, but a full generation for Intel)
7950X and 13900K/S will be as good as medium sized Workstation CPUs(Zen3/Alder Lake 24/32 low clocked)
For general purpose computer yes, absolutely. Also take into account that Intel SPR has SDSi where if you need AVX512 and AMX you will have to pay to unlock them. And on Zen4(Ryzen 7/9) they will be standardThey will be, because there wont be anything better (for acceptable price).
Source?take into account that Intel SPR has SDSi where if you need AVX512 and AMX you will have to pay to unlock them.
YuuKi_AnS, his QS sample 8480+(56C/112T) and 8490H(60C/120T) have it disabled by Paid For Software Lock.Source?
Doesn't mean all SPR chips would be the same. That's very much a server thing, and probably doesn't even apply universally there.YuuKi_AnS, his QS sample 8480+(56C/112T) and 8490H(60C/120T) have it disabled by Paid For Software Lock.
While YuuKi_AnS only works with 2S, 4S and 8S system. I find it strange that the Server CPUs will have AVX512/AMX Disabled by SDSi and the Xeon W9 series will not...!Doesn't mean all SPR chips would be the same. That's very much a server thing, and probably doesn't even apply universally there.
The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?
I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.Nah it's still SPR. Just a reduced core count but most of the L3 still intact.
I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.
That's an interesting find. Provided it's being read correctly, I can believe it's Emerald Rapids. Don't see why monolithic SPR would have any more L3/core than chiplet. Will certainly be interesting to see what the die looks like.Look what I just found...!!
Details for Genuine Intel CPU 0000%@32C/64T 1.7GHz, 900MHz/2.2GHz IMC, 32x 2MB L2, 90MB L3
The 90 MiB L3 per 32C would put this past the 1.875 limit of Sapphire Rapids Xeon Platinum and W9 models we have seen so far. Is this the Elusive Monolithic Design or Emerald Rapids?
Dont put too much weight on early Geekbench results. The First ones for Genoa were dismal, but that's because Geekbench. The very early results are good to see uArch info.I don't have geekbench numbers memorized. Is 21, 799 for 192 threads good ? does not sound like it.
I just looked. 2 32 core 64 thread (128t total) Zen 4 was 57,xxx (something), so 21799 for 192 is dismal.
I have never seen this kind of segmentation done by Intel, when they disable cores, they also disable the half ring connected to that core, that is done to reduce Power and performance latencies penalties.. The Leaked SKUs do not show any other SPR with higher MiB per core.
Ian gets to the main point.
Less talk, more action, Intel.
Pretty sure we've already established that launch SPR silicon for the majority of the market is E5 stepping, no?
Pretty sure we've already established that launch SPR silicon for the majority of the market is E5 stepping, no?
They better start shipping it H2'23. There's really no excuse for effectively a refresh product to take longer than a year.Perhaps Emerald Rapids is on track for a Q2 2024 Release?