It's a little bit more than a Refresh. They have Raptor Cove P cores on it. Larger Cache and Larger Compute Tile(64C/128T) Total, Larger HBM2e. All of those need validation.
They better start shipping it H2'23. There's really no excuse for effectively a refresh product to take longer than a year.
Ian has become a lot more thorny after he left anandIan gets to the main point.
It's Dr. Ian Cutress for you.Ian has become a lot more thorny after he left anand
I don't think there've been rumors about EMR-HBM, but that matter aside, all of those features are pretty minor. The biggest thing will probably be full CXL support, but it's humiliating that it's not functional on SPR to begin with. GNR will be the first real chance for Intel to show improvement.It's a little bit more than a Refresh. They have Raptor Cove P cores on it. Larger Cache and Larger Compute Tile(64C/128T) Total, Larger HBM2e. All of those need validation.
It's Dr. Ian Cutress for you.
Now that seems like a far more sane result than some of the earlier ones that were being posted.New Benchmarks for 2S Sapphire Rapids, more or less on par with Milan
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Intel Xeon Platinum 8468 48 Core "Sapphire Rapids" CPU Benchmarks Leak, On Par With AMD's 64 Core Milan Chips
Benchmarks of the Intel Xeon Platinum 8468 48-Core Sapphire Rapids CPU have leaked out which show competitive performance versus AMD's Milan.wccftech.com
Yes, I agree. But I blame that on Buggy Bios, Buggy MB and plain old Buggy ES Sample SPR.Now that seems like a far more sane result than some of the earlier ones that were being posted.
They don't, but they don't have to, if they cater niche customers that will use HBM/AI/AMX, we know that the IPC is on Par but low clocks and low core counts means AMD will beat them at absolute performance and CTO. 4S and 8S are super Niche now.Given the above mentioned SPR benchmarks, I'm not seeing how these "leaked" Emerald Rapids specs really move the needle much against Genoa and Bergamo?
No, it's just an additional Core.How much bigger is Emerald going to be? 500 mm2 per tile?
No, it's just an additional Core.
Emerald Rapids will have total of 16C per tile as opposed to SPR-SP 15(16 but one is the IMC) So they need to at least have 17 core sized unit per tile.
No, it's not just more cores per tile.No, it's just an additional Core.
Emerald Rapids will have total of 16C per tile as opposed to SPR-SP 15(16 but one is the IMC) So they need to at least have 17 core sized unit per tile.
That is true, I was over simplifying it. Now that I think about it. It's going to be a rather large Compute tile capable of 19 active cores(the 20th is the IMC) but due to yields perhaps at this stage they will top at 16 Active cores..No, it's not just more cores per tile.
Oh I understood what you meant. I'm just saying that that topology doesn't make sense. Why add an extra row just to enable one more core? Why have more redundancy/dead silicon than SPR?That is true, I was over simplifying it. Now that I think about it. It's going to be a rather large Compute tile capable of 19 active cores(the 20th is the IMC) but due to yields perhaps at this stage they will top at 16 Active cores..
Emerald Rapids Mock Up with three disabled Cores
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Someone mentioned that it could be due to yields, but it's rather a small tile(20 core sized tile, one for IMC and others disabled) I don't see that happening. How would an additional core be activated on a tile that has 16 sized cores and one being for the IMC?Oh I understood what you meant. I'm just saying that that topology doesn't make sense. Why add an extra row just to enable one more core? Why have more redundancy/dead silicon than SPR?
That's precisely the question. So what's the alternative if another row of cores added to the existing die doesn't seem to work?How would an additional core be activated on a tile that has 16 sized cores and one being for the IMC?
There is no other way to add another core to the existing 400mm2 Tile on the same process node.that design was locked 4 years ago.What's the alternative if another row of cores added to the existing die doesn't seem to work?
If they can make a number of SKUs with 14/15 cores in 2022, then there's really no reason that they can't manage better than 15/19 in 2023.Maybe 76 was the intent but getting 16-19 core tiles is too rare to make an SKU out of it. They could sell sell the ones they do get off label.
There is no other way to add another core to the existing 400mm2 Tile on the same process node.that design was locked 4 years ago.
My point here has been that you're starting with the assumption that they're taking the existing 4 tile topology and doing something to it to add another core, and then spending a lot of mental effort to come up with a sensible something. Instead, perhaps reconsider the original assumption.Locuza believes that Intel could have just move around a few things on that 400mm2 tile to add just one more core.
Given the above mentioned SPR benchmarks, I'm not seeing how these "leaked" Emerald Rapids specs really move the needle much against Genoa and Bergamo?
I don't think any sane person believes Emerald Rapids will be enough to compete with Genoa, nor have I seen that suggested thus far. But if it's better than SPR, it still holds value.I Still think that 64 Cores Will not cut it till late 2024 early 2025
If they can make a number of SKUs with 14/15 cores in 2022, then there's really no reason that they can't manage better than 15/19 in 2023.