Please stop trying to Spin that for Intel. It was HBM and it's even in their own manual.It was HMC (Hybrid Memory Cube).
How is that a spin? HMC was different tech, pushed by Micron and Intel, while HBM was mostly SK Hynix and AMD.Please stop trying to Spin that for Intel. It was HBM and it's even in their own manual.
MCDRAM as High-Bandwidth Memory (HBM) in Knights Landing Processors: Developer’s Guide
This publication is part of a developer guide focusing on the new features in 2nd generation Intel® Xeon Phi™ processors code-named Knights Landing (KNL). In this document we discuss the…colfaxresearch.com
"High Bandwidth Memory" was previously (and in some uses, still is) a generic term for multiple underlying technologies, including both HMC and what we now call just "HBM". I certainly agree that it's confusing to have the same term for both a generic and specific implementation, but nothing to be done now.So all of the researchers, scholars and all of the documentation(even from Intel) that say Knights Landing HBM/MCDRAM are wrong? Doing the simplest google search will attest to this.
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The thing is. Intel went out of their way to call this product "The First and Only X86 CPU with HBM" When even their own official documentation was using HMBI certainly agree that it's confusing to have the same term for both a generic and specific implementation, but nothing to be done now.
However, basically, I think that EMRs with HBM3 should compete Genoa-X.
They are banking on 4S to bring core parity.At 56C vs 96 and a node disadvantage they will be at more than 100% higher CPU power at equal throughput
This is factually correct
It does, being second on any metric is actually not regarded as highly.1st or 2nd is not matter.
In a word, Intel said that "EPYC w/o HBM should lose its share in HPC market".
They are banking on 4S to bring core parity.
At 4S They will have 224C/448T while Genoa will have a max of 192C/384T
There is no doubt that 10nm Golden Cove is less efficient than 5nm Zen4 in general purpose apps(and I suspect in AVX-512), but on niche HPC workloads those Accelerators that take advantage of HBM2e will give The Xeon Max a substantial advantage. Regular Xeon Platium based on Sapphire Rapids and Workstation CPUs do not enjoy such advantage so Genoa being a more general purpose CPU will Rein Supreme at the highest level.At 224C they ll have to consume at least 2x the power to match a theorical 224C Zen 4
DT workloads are apple.
HPC workloads are orange.
To give an example, Intel claims that...
> Intel® Xeon® CPU Max Series-based clusters using HBM only,
> consume 68% lower power for their CPUs and memory to achieve
> equivalent performance to a cluster using AMD EPYC 7773X
They might have different limits for normal SPR vs with HBM, so that will be interesting to see when they release the rest of the lineup.Now that I see the details... Here is what most stood up.
Max Core Count: 56 Per Socket, 2 sockets being the most supported(giving AMD 2S the advantage in core count).
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Rumors have indicated Intel will be releasing HEDT Sapphire Rapids (sorry if I misunderstand what you are implying). Even if AMD's chip is faster, Intel's chip is uh...Intel (couldn't figure out how to word that! 🤣), and people will buy it. Furthermore, if it has competitive pricing, it could potentially sell very well. Shoot, if the price is right, I, myself, may buy SPR-S. All they have to do is beat AMD at total platform cost. Of course, it is Intel.There is a Zero Chance that Intel will release such CPU, just to be trampled by AMD Zen3 5995WX..
You guys focus way to much on the 1s or 0s of yields. It isn't "chip works" or "chip doesn't work". It is "chip works at full spec", "chip works at xyz spec" or "chip doesn't work and isn't sellable". A chip can have a yield of 60% and 90% of the dies can still be in working condition. Intel and AMD both deal with this, and these cut down chips are priced accordingly (lower core count, lower cost. Perfectly specced chips have a premium added on to balance the lower or negative margins on the "defective" chips)No, 40 fully functional dies means that they can then attempt to package 10 CPUs at 60% lithography yield. This says nothing about their packaging success rate, which we know will not be 100% if industry history is to be believed. It is highly likely that packaging will cost them a few percent more losses in start to finish yield.
Yes, it will add up and cloud vendors will be more inclined to purchase AMD chips. That is actually already happening, however when Genoa and Genoa-X drop, Intel is going to have a rather large problem on their hands.and 1/2 that for Genoa at the same performance. You think data centers are going to deal with that without considering Genoa ? Power nowadays is king. Not just me, its a real consideration now.
For high core counts, more power will be used, yes, but unfortunately for Intel, AMD will have them beat on perf/watt.Genoa is going to use more power than that per socket, depending on the SKU. We'll get a better idea of the exact numbers later, but assume that Genoa can use up to 350-400W per socket.
2S-8S. However, again, perf/watt is an issue. Don't get me wrong, Intel is going to sell quite a few chips just from being...uh...Intel, however I suspect SPR-S won't be the best selling Xeon, nor will it have the best margins, and thanks to all the flubs/steppings, their budget is probably blown to shreds.They are banking on 4S to bring core parity.
At 4S They will have 224C/448T while Genoa will have a max of 192C/384T
So all of the researchers, scholars and all of the documentation(even from Intel) that say Knights Landing HBM/MCDRAM are wrong? Doing the simplest google search will attest to this.
Max Core Count: 56 Per Socket, 2 sockets being the most supported(giving AMD 2S the advantage in core count).
Correct, I was specifically referring to Xeon Max. Then non-HBM SPR-SP will support 8SXeon Max is likely the brand for HBM enabled Sapphire Rapids. They are targetted for HPC and usually do not support high socket configurations.
> Intel Xeon Max ‘Sapphire Rapids HBM’ CPUs Specs & Prices Leak Out: Xeon Platinum 9480 Flagship With Up To 56 Cores at $12980 US
Intel Xeon Max 'Sapphire Rapids HBM' CPUs Specs & Prices Leak Out: Xeon Platinum 9480 Flagship With Up To 56 Cores at $12980 US
Intel's Xeon Max 'Sapphire Rapids' HBM CPU lineup specifications and pricing has leaked out showcasing up to 56 cores at $12980 US.wccftech.com
Intel's official prices are so fake that it's not even worth discussing.