Not to mention trying to compare Zen4c to E-cores (not in the same class) and saying "hybrid solutions are the future" when only Intel has done it (aside from iphones and the like) Even arm stays with all the same cores that I have seen.Again, BACK ATCHA. You're ignoring Intel's recent inability to execute and leaning on products that don't even exist yet, and may never on the broader market! You keep pumping up e-cores in contrast to cores that are known to have area and power-efficiency problems. There is no "arguing in bad faith".
This is precisely what I'm talking about. The discussion was on the inherit merit of small cores vs big ones for certain markets. Now you're trying to twist it into being about Intel's execution issues, which you don't even bother to connect to the subject of small cores. There is no discussion to be had with someone who changes their argument with every reply.Again, BACK ATCHA. You're ignoring Intel's recent inability to execute and leaning on products that don't even exist yet, and may never on the broader market! You keep pumping up e-cores in contrast to cores that are known to have area and power-efficiency problems. There is no "arguing in bad faith".
According to the which set of made up numbers now?Not to mention trying to compare Zen4c to E-cores (not in the same class)
Of the consumer application processor market, the majority is ARM, almost all of which are hybrid. Of the remainder, the vast majority are Intel, which is also all-in on hybrid. So no, hybrid solutions are not the future. They are the present.and saying "hybrid solutions are the future" when only Intel has done it (aside from iphones and the like) Even arm stays with all the same cores that I have seen.
Zen4c for one has avx-512, which e-cores do NOT. Not to mention benchmarkwise they are not even in the same class.According to the which set of made up numbers now?
Of the consumer application processor market, the majority is ARM, almost all of which are hybrid. Of the remainder, the vast majority are Intel, which is also all-in on hybrid. So no, hybrid solutions are not the future. They are the present.
And since when did that matter for the cloud market these chips are targeting?Zen4c for one has avx-512, which e-cores do NOT.
Where are you comparing benchmarks for not one, but two unreleased products?Not to mention benchmarkwise they are not even in the same class.
So aside from the billions of devices that use hybrid? No one was suggesting it for servers.As for the hybrid, would you care to list all the hybrid CPU's that are NOT for phones or Apple that are hybrid ? Like real server CPUs ?
The penalty for Intel-sided fusion of processors into a monolithic virtual core is between 90% to 98% of the fictional monolithic core.It looks AMD CMT processors with additional Inter-core resources to me. Will it really perform well in ST workloads compared to vanilla BF OOO cores? I agree if they are planning to mitigate ST degradation due to small core sizes, but not sure if it's really the way to boost ST performances.
Way to avoid my question. I was not even replying to your originally, just agreeing with another member. I should know better than to trade posts with you as you always avoid my questions, or change the subject. I am done with you....And since when did that matter for the cloud market these chips are targeting?
Where are you comparing benchmarks for not one, but two unreleased products?
So aside from the billions of devices that use hybrid? No one was suggesting it for servers.
Not to mention benchmarkwise they are not even in the same class.
Hmm, where do you think the i9 13900k will sit in MT, non AVX 512 performance? I'm guessing around W5-2465X - W5-2475X ?Looks like the specs of the new Sapphire Rapids based Xeon-W line have leaked ahead of the launch event today.
ranging from 6-56 cores, 64-112 PCIe Gen5 lanes and quad or octo channel configs.
56 core price tops out at $5889
Intel Xeon W3400/2400 specs and pricing leaks out, 56-core Xeon W9-3495X to cost $5889 - VideoCardz.com
Intel Sapphire Rapids for workstation The full specifications and pricing has been confirmed by Chip website. Intel Xeon Sapphire Rapids Workstation, Source: Chip.cn The flagship 56 core Workstation CPU will cost $5889, while the most expensive W2400 part will retail at $2189, confirm leaked...videocardz.com
Looks like the specs of the new Sapphire Rapids based Xeon-W line have leaked ahead of the launch event today.
ranging from 6-56 cores, 64-112 PCIe Gen5 lanes and quad or octo channel configs.
56 core price tops out at $5889
Intel Xeon W3400/2400 specs and pricing leaks out, 56-core Xeon W9-3495X to cost $5889 - VideoCardz.com
Intel Sapphire Rapids for workstation The full specifications and pricing has been confirmed by Chip website. Intel Xeon Sapphire Rapids Workstation, Source: Chip.cn The flagship 56 core Workstation CPU will cost $5889, while the most expensive W2400 part will retail at $2189, confirm leaked...videocardz.com
These are still made from one large piece of silicone and are not cheap to make at all. They may have an advantage of lower core to core latency than Threadrippers. They may actually force AMD to lower the price of Threadrippers somewhat.So 24 core costing about as much as 24 core TR 5965X? Color me surprised. The joy of duopoly and fake competition.
Plus, you would have gotten stuck with no upgrade path if you went with workstation CPU. Now you can enjoy increased performance in 4 or 5 years with a CPU upgrade without having to change the whole system.i did right choice going with 7950x.
These are still made from one large piece of silicone and are not cheap to make at all. They may have an advantage of lower core to core latency than Threadrippers. They may actually force AMD to lower the price of Threadrippers somewhat.
You can pay for two larger pieces of silicone for less than one of those W9's, and probably get a lot more enjoyment out of them.These are still made from one large piece of silicone and are not cheap to make at all. They may have an advantage of lower core to core latency than Threadrippers. They may actually force AMD to lower the price of Threadrippers somewhat.
The W9 3495X will Support AVX-512 and AMX
It looks AMD CMT processors with additional Inter-core resources to me. Will it really perform well in ST workloads compared to vanilla BF OOO cores? I agree if they are planning to mitigate ST degradation due to small core sizes, but not sure if it's really the way to boost ST performances.
I have read the E cores are actually "Cinebench accelerators." While funny, there is some truth to that statement as there aren't a lot of applications that will fully utilize all 16 E's in a 13900 series part.
This is probably the real reason why Arrowlake is going to be 8+16 rather than 8+32. There were rumors while ago that ARM cores in phones/tablets would go up quickly to 16+ cores. It hasn't.
There are tasks which can use all the cores/threads you can throw at them. Some rendering/encoding tasks. What I do can use all the cores/threads 24/7, but DC is the only place you will see that.Most software has yet to catch up to CPU's with 16 threads must less 32 or more.
The original Bulldozer design was also a proper clustered-based multithreading arch. The boss of cores at the time wanted to reduce Opteron power and increase core counts with many 2 GHz low-power/high-IPC cores. Bulldozer 2007's HPC 16c = 16-actual processors and 32-int-clusters.There were rumors a while ago the original Nehalem was a "proper" CMT CPU aimed at increasing performance rather than saving area per thread as with Bulldozer.
David Witt(Chief for K8 generation secondary design) => 1997 homo-clustered architecture (Two monolithic clusters each with Int/FPU//LD/ST)
Jim Keller => 1999 hetero-clustered architecture (Three clusters, one with Int, one with FPU, one with LD/ST:;Proto-Bobcat // handled by the converted MIPS->x86 Alchemy team with Brad B.(Chief Arch(Bobcat))/McKinney(Chief Tech(Bobcat&Bulldozer))
Andy Glew => 2002-2004 K10 architecture (Independent from the above, but spinned out from LP-project::clusters are not yet cores)
Charles R. Moore => 2005-1H2007, Original Bulldozer architecture (Derived from Witt/Keller with four clusters: Two Int(CMT2), One LD/ST(SMT2), One FPU(SMT2)::Bulldozer)
Mike Butler => 2H2007-2013, K10 as "Bulldozer" (Derived from Glew's microarchitecture at AMD::clusters became cores)
Glew/Butler Architected design focused towards high performance => higher frequency
"Perhaps I should say here that my MCMT had a significant difference from
clustering in, say, the Alpha 21264,
Those clusters bypass to each other: there is a fast bypass within a
cluster, and a slightly slower (+1 cycle) bypass of results between
clusters. The clusters are execution units only, and share the data
cache. This bypassing makes it easy (or at least easier) to spread a
single thread across both clusters. My MCMT clusters, on the other
hand, do NOT bypass to each other. This motivates separate threads per
cluster, whether explicit or implicit."
Boss of Glew "K10 Architect" and Butler "K10 as Bulldozer Architect" wanted high frequency. As well not implementing SpMT or anything complex which could comprise frequency.
Moore Architected design focused towards low power and scalability => higher IPC(TLP->IPC[MT] and ILP->IPC[ST])
Boss of Moore's time as OG Bulldozer Architect wanted low power.
New naming scheme of ongoing AMD development;
HP1(launched) -> HP2(launched) -> HP3(dropped:2012->2013) // HP3 ST had access to 8 add/inc/dec/etc ALUs
LP1(hiatus:2014->2018) // Started while StoneyX was being done. FT4 socket was suppose to be Excavator and LP-NextGen(LP1).
ULP1(restart:LP1, resume on new target node:2019->2023]