The Bulldozer core that launched was based off K10 is thus part of Weber's 2003 roadmap:
2005(expected) => K9 Alsup
2007(expected) => K10 Glew
Q4 2004~2005 Fred Weber announced K9/K10 being dropped and leaves AMD.
The only core AMD has that isn't based on prior cores is Bobcat. So, when the IBM crew came in 2005 they opt for Bobcat to act like GPUL(PowerPC970) and Bulldozer to act like GP(POWER4).
Bobcat, >1 GHz:
Integer Scheduler/Cluster | Address Scheduler/Cluster | FPU Scheduler/Cluster |
2x I-Pipes | 1x Ld-pipe + 1x St-pipe | 1x A-pipe + 1x M-pipe |
Bulldozer(original), ~2 GHz:
Integer Scheduler0/Cluster | Integer Scheduler1/Cluster | Address Scheduler/Cluster | FPU Scheduler/Cluster |
2x I-Pipes | 2x I-pipes | 3x Ld+St-pipes | 4x FP-pipes *unsure of unit layout* |
Clustered Microarchitecture(ST-focus first) -> Cluster-based Multithreading means each critical-path (general purpose/control) cluster gets a thread and everything else is SMT2.
K10 as Bulldozer(launched), ~3.5 GHz:
Unified Scheduler0/Core | Unified Scheduler1/Core | FPU Scheduler |
2x EX-pipes + 2x AGLU-pipes | 2x EX-pipes + 2x AGLU-pipes | 2x FMA (2x~64b Hi/Lo) + 2x MMX (2x64b Hi/Lo) |
Kept most of MCMT, but at launch converted towards Chip-level Multithreading.
Basically, have to track two different "CMT" implementations. One for the Moore's Bulldozer(Work up from Bobcat) and one for the Butler's Bulldozer(Work onto K10).
Weber(cores):
Hester(cores):
Weber[K10] -> Hester[Bulldozer] -> Meyer[K10 w/ Bulldozer bits]