Discussion Intel current and future Lakes & Rapids thread

[Glo.]

(Just to be clear, the excuse I'm giving is for MLID. He did get some things right. RGT is whole another level of nonsense)

Yep. Especially the one information about 128 MB Infinity Cache on Navi 21 GPU information from Paul was incorrect. Turned out to be complete BS.

Before anyone chime in. It was Paul who got this information publicly first, and even then NOBODY believed in it.

 

[Saylick]

Yep. Especially the one information about 128 MB Infinity Cache on Navi 21 GPU information from Paul was incorrect. Turned out to be complete BS.

Before anyone chime in. It was Paul who got this information publicly first, and even then NOBODY believed in it.

I'll give him credit for that, but the signal to noise ratio is far from ideal. Even a broken clock is right twice a day, and a blind squirrel can find a nut every once in a while.

 

[NostaSeronx]

Ah 2006 the early multi-core era combined with the Conroe hype spawned many rumors. AMD was just about to response with the core-merging tech.

AMD reverse multi-threading tech 'does not exist'

Someone misunderstood virtualisation?

www.theregister.com

"One said it represents a misunderstanding of another technique, though (s)he didn't elaborate."

I assume this is one of the issues of cluster-based multithreading. Where the original technique that AMD was going for was fusing mid-core/execution cores;
(Each Execution Core had Int/AGU/FPU;; Single-threaded only // 1997)

(FPU was pushed out;; Single-threaded only // 2001)

AMD after 2003 the patents disappeared before coming back as Butler's modification for late 2007-early 2008. However, there is a patent out their that implies two 126A execution cores for Integer, 126B execution core for FPU, and 126C execution core for AGUs+Load/Store[AGUs pushed out into their own scheduler like Bobcat/Jaguar: https://www.realworldtech.com/jaguar/6/] // 2003 & 2005. The only sign of Moore's core is the open64 patch:



Distinct physical mid-core slices that can fuse into one virtual large mid-core slice, etc. However, this is technically wrong since it was built in mind for single-threaded w/o the penalty of monolithic growth.

2 ALUs = Full Speed
4 ALUs = Half Speed
2+2 ALUs = 3/4th Speed on same node and full speed on next node, etc.

This is also shown in centralized LSUs and clustered LSUs:

Centralized is a single unit :: Distributed is four units

Revisiting clustered microarchitecture is a 2015 thing and there is several prior projects funded by Intel to combine tiles(multiple cores w/ single L2 -> single larger core w/ single L2). However, from what I can tell the P-core project was dropped to support Haifa's Bogstandard Monolithic P-core and the fuse group was moved to the E-core projects. It is not a cove core, and is only a mont core. Lion Cove/Panther Cove != E-cores.

P-cores[P-core Chief @ Haifa, sub-teams all over] => Designed for high Speed [Large Area: relative to E-core], not okay to have high latency.
E-cores[E-core Chief @ Austin, sub-teams all over] => Designed for low Voltage [Small Area: relative to P-core], okay to have high latency so long output is high.

 

[Glo.]

I'll give him credit for that, but the signal to noise ratio is far from ideal. Even a broken clock is right twice a day, and a blind squirrel can find a nut every once in a while.

Getting something as specifc as 128 MB L3 cache size is not something that broken clock would point correctly, nor would blind squirrel find once in a while.

Paul can be blamed for a lot of things. But he should not be blamed for missing perf. targets by engineers, who actually were working on the hardware.

 

[Exist50]

Paul can be blamed for a lot of things. But he should not be blamed for missing perf. targets by engineers, who actually were working on the hardware.

No AMD engineer ever claimed a 2.5x perf target. I don't see why you continue to defend this guy lie after lie.

 

[yuri69]

Getting something as specifc as 128 MB L3 cache size is not something that broken clock would point correctly, nor would blind squirrel find once in a while.

Paul can be blamed for a lot of things. But he should not be blamed for missing perf. targets by engineers, who actually were working on the hardware.

I've used my free 1.5h to skip though at least some RTG YT videos concerning AMD products labeled as his "exclusives" and "leaks".

It's truly a hilarious example of today's YT content.

2022-04-17​	RDNA 3 CHANGES EVERYTHING - Specs Chiplet Config & Performance | Zen 5 EARLY Info & Future APUs​	N31 1-2k USD MSRP; MCD capacity 256-512MB N31 is 3x RX 6900XT in FP32 N31 is 3-4x of N21 in RT Navi 3 use PCIe 5 N33 4096 shaders @2.8-3GHz Phoenix RDNA2 with 16+CUs
2022-04-28​	AMD Phoenix DESTROYS Budget GPUS​	Phoenix on 5nm TSMC; 1536 shaders​
2022-04-30​	RDNA 3 Hits OVER 3GHz With INSANE Architecture​	N31 2 GCDs, 4 MCDs on top of GCDs, 120 Cus (15360 shaders), PCIe 5, 256b mem, 512MB IC N33 4096 shaders, 3.2GHz, PCIe 5
2022-04-09​	Zen 4 Phoenix Is RIDICULOUS​	Phoenix on 5nm TSMC – 1536 shaders at 3GHz; PCIe 5; 60W TDP​
2022-05-13​	Zen 4 5.2GHZ BENCHMARK & IPC Gains LEAK |​	Raphael 16c up to 5.4GHz and 8c up to 5.2GHz​
2022-06-24​	AMD Phoenix - A Zen 4 & RDNA 3 MONSTER​	Phoenix “chiplet design with CPU+GCD+MCD”, 1536 shaders at 2.6-3GHz; 60-70W TDP; PCIe 5​
2022-07-05​	RDNA 3 MCD & Memory Config CONFIRMED​	N31 12288 shaders; 2.1-2.5x conservative and 3.5x RT of N21; PCIe 5 a 2 GCDs N31 variant N33 4096 shaders; PCIe 5
2022-08-07​	RDNA 4 Is a GPU REVOLUTION​	N31 “RX 7950XT” – 84 CU, 405W TDP for top reference, 1500 USD MSRP​
2022-10-17​	RDNA 3 - Is Nvidia IN TROUBLE?​	N31 – 12288 shaders at 3.3GHz, 81 TFLOPS, “overclocks quite well”; N33 – 4096 shaders at 3-3.5GHz, PCIe 5​
2022-11-01​	RDNA 3 Power Efficiency Is INSANE​	RX 7900XTX “incredibly energy efficient”​

 

[nicalandia]

Intel Xeon 8450H(2S 56 Cores Total). Cinebench R23 MT: 52,600 Points.

DogFace`s Cinebench - R23 Multi Core with BenchMate score: 52599 cb with a Xeon Platinum 8450H

The Xeon Platinum 8450H @ 2600MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. DogFaceranks #12 worldwide and #1 in the hardware class. Find out more at HWBOT.

hwbot.org

That is a stock Xeon Platinum 8450H.

 

[Hitman928]

Intel Xeon 8490H(2S 120 Cores Total). Cinebench R23 MT: 52,600 Points.

View attachment 76886

DogFace`s Cinebench - R23 Multi Core with BenchMate score: 52599 cb with a Xeon Platinum 8450H

The Xeon Platinum 8450H @ 2600MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. DogFaceranks #12 worldwide and #1 in the hardware class. Find out more at HWBOT.

hwbot.org

Isn’t it 112 cores total? That’s a pretty awful score for such a CPU. Something has to be wrong.

edit: looks like it’s 56 cores total, 28 per socket. Even still, doesn’t seem like a good score.

 

[nicalandia]

Isn’t it 112 cores total? That’s a pretty awful score for such a CPU. Something has to be wrong.

edit: looks like it’s 56 cores total, 28 per socket. Even still, doesn’t seem like a good score.

Sorry, I thought it was the 8490H, but it's the 8450, so 56 Cores total.

 

[Markfw]

Isn’t it 112 cores total? That’s a pretty awful score for such a CPU. Something has to be wrong.

edit: looks like it’s 56 cores total, 28 per socket. Even still, doesn’t seem like a good score.

yes, when a Genoa 32 core does 50,000

 

[IntelUser2000]

I've used my free 1.5h to skip though at least some RTG YT videos concerning AMD products labeled as his "exclusives" and "leaks"

Shame on him. Lies one after another. I wouldn't categorize RGT as baiting anymore. He's plain lying. Based on how often it happens I question the person himself. I'd view it as social media evidence future employers would use to caution from hiring this guy.

However Youtube can be whatever you want and even ridiculous lies you can get millions of views over dozens of videos and channels. If you want any decent number of views on Youtube you also have to play the baiting game. That's why videos have bolded, font 30 letters with exclamation marks as the thumbnail. It has been proven doing it increases views by 2-4x.

Yes you can get good stuff on Youtube but you have to know what you are doing. If you know crap, then you'll likely search for crap.

 

[Geddagod]

Well I hate to agree with MLID on much of anything...

https://twitter.com/x/status/1627899433865338880

But many leakers also seem to be claiming MTL is mobile only at this point. The combination of recent leaks, and rumors of RPL-R, basically convinced me that MTL is mobile only. Just my opinion though!

 

[poke01]

Well I hate to agree with MLID on much of anything...

https://twitter.com/x/status/1627899433865338880

But many leakers also seem to be claiming MTL is mobile only at this point. The combination of recent leaks, and rumors of RPL-R, basically convinced me that MTL is mobile only. Just my opinion though!

Nothing wrong with that. It's Intels first chiplet arch for the mainstream in volume.

Hopefully Intel is ready to release chiplets SoCs by 2024 with arrow lake on desktop otherwise AMD will cream them on desktop.

Edit: changed CPUs to SoCs cause of arrowlake(fight me )

 

[jpiniero]

Intel defers placing 3nm chip orders with TSMC

Intel will delay placing orders for 3nm chips with TSMC until the fourth quarter of 2024, according to sources at PC makers.

www.digitimes.com

Digitimes claims Intel has pushed out their N3 order to the end of 2024. Looking like Raptor Lake Refresh will get a full cycle on desktop.

 

[igor_kavinski]

Looking like Raptor Lake Refresh will get a full cycle on desktop.

Why do I get the feeling that we will see a re-enactment of the Comet Lake vs. Zen 3 debacle? Unless AMD really drops the ball, Zen 5 will trample all over RPL-Refresh.

 

[deasd]

Why do I get the feeling that we will see a re-enactment of the Comet Lake vs. Zen 3 debacle? Unless AMD really drops the ball, Zen 5 will trample all over RPL-Refresh.

We still don't know when will Zen5 launch, but even before that, Intel has to face Zen4 X3D first....

 

[igor_kavinski]

We still don't know when will Zen5 launch

Should be sometime in 2024 unless AMD decides to slack off and not embarrass Intel.

 

[Kocicak]

... Unless AMD really drops the ball, Zen 5 will trample all over RPL-Refresh.

Why talk about one refresh? There may be more of them... Some of them can be surely good, no?

 

[igor_kavinski]

Why talk about one refresh? There may be more of them... Some of them can be surely good, no?

RPL++++

 

[Kocicak]

If the Raptor refresh will be 6+8+large GPU, I would be pretty mad, because that is exactly what I want. Selling 12600K was a bloodbath, I sold it with DDR4 RAM and I lost 45% of what I payed for those parts. If I add losses of selling my current 13600K.... Damn. What am I doing....

 

[Hulk]

Why do I get the feeling that we will see a re-enactment of the Comet Lake vs. Zen 3 debacle? Unless AMD really drops the ball, Zen 5 will trample all over RPL-Refresh.

When is Zen 5 due? Looks like Intel is stuck on 10nm. Hopefully not as stuck as they were on 14nm.

I miss typing the ++++++++'s.

Let's see Alder was 10nm, Raptor 10+, and the refresh will be ++. Not enough plusses to hold down the key like the old days but we're getting there.

Maybe a back port of Meteor to 10+++ is in the cards?

While I am a longtime Intel user if they do get stuck on 10nm and Zen 5 comes out on time and is a killer it will be fun to watch them try to talk their way out of how history is repeating.

 

[jpiniero]

Let's see Alder was 10nm, Raptor 10+, and the refresh will be ++. Not enough plusses to hold down the key like the old days but we're getting there.

Alder Lake is 10+++.

 

[uzzi38]

Nothing wrong with that. It's Intels first chiplet arch for the mainstream in volume.

Hopefully Intel is ready to release chiplets SoCs by 2024 with arrow lake on desktop otherwise AMD will cream them on desktop.

Edit: changed CPUs to SoCs cause of arrowlake(fight me )

It being mobile focused is nothing to do with it being their first attempt at chiplets.

MTL/RWC just isn't good enough to be worth bringing to desktop. ST perf gains just ain't there against desktop RPL.

EDIT: Also I have no clue what the whole CPU+SoC+IO die thing is all about. That's just nonsense.

 

[Geddagod]

It being mobile focused is nothing to do with it being their first attempt at chiplets.

MTL/RWC just isn't good enough to be worth bringing to desktop. ST perf gains just ain't there against desktop RPL.

EDIT: Also I have no clue what the whole CPU+SoC+IO die thing is all about. That's just nonsense.

Ye didn't find the time until now to type it up but...
I heard some people talking about how they couldn't have made he CPU+SoC+IO die on Intel 4 anyway because it only has HP libs.
Idk if you have to have HD cells or separate cells for IO and such. Obviously it would be preferable to save the area by using HD cells or something, but I am uncertain if you can't use HP cells at all for IO and such.
I still don't believe that leaked diagram is true btw, I just don't know if the fact Intel 4 only has HP libs is the reason for it.
Also, if MTL launches end of 2023, when should we start seeing ES samples again? 3Q?

 

[uzzi38]

Ye didn't find the time until now to type it up but...
I heard some people talking about how they couldn't have made he CPU+SoC+IO die on Intel 4 anyway because it only has HP libs.
Idk if you have to have HD cells or separate cells for IO and such. Obviously it would be preferable to save the area by using HD cells or something, but I am uncertain if you can't use HP cells at all for IO and such.
I still don't believe that leaked diagram is true btw, I just don't know if the fact Intel 4 only has HP libs is the reason for it.
Also, if MTL launches end of 2023, when should we start seeing ES samples again? 3Q?

I would say much sooner than that.

Well I mean until those samples are outside of Intel. It might take a while until WE actually see anything about them though.