Discussion Intel current and future Lakes & Rapids thread

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Hulk

Diamond Member
Oct 9, 1999
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Just a nitpick but Pentium M is more derived from Pentium III than 4.

Absolutely correct. Core was the next desktop architecture after P4, which is why I specified it as next in line after P4 chronologically, not architecturally as you correctly pointed out.
 

Hulk

Diamond Member
Oct 9, 1999
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I doubt that Raptor Lake Refresh (if any) would be on Intel 4. If it were, be prepared for disappointment since there might be clockspeed regression.

I agree, no way RLR will be Intel 4. It's currently being "born" from the excellent yields they are getting on Intel 7 with perhaps some small structure changes.

Problem... or expected difficulty. Scaling down past where they currently are is getting massively more difficult. Witness other leading foundaries having their own problems with achieving better total processes and many others just throwing in the towel along the way. As it stands, all of the foundaries on the leading edge are essentially peddling half and quarter steps between node variants to eek out even the tiniest of improvements to fill the long gaps between full nodes. I don't see Intel as being in trouble as much as I see the crowd catching up to them and occassionally gaining a small lead. We may bag on Intel's 10nm process, but it was often within spitting distance or even better than competing nodes for absolute circuit density. When fed reasonable power, it returned reasonable performance that improved with each revision.

If you think Intel is doing so much worse, look at their competition. Samsung has struggled to stay within a full node of TSMC and Intel, underperforming all along the way for years. TSMC is experiencing delays and having to issue less aggressive subnodes on N3 (N3e being one) to keep customers happy. Who else is anywhere near these three?

Intel's schedule is, as usual, overly optimistic. They aren't falling behind on process tech though.

Good points and they lead me to the conclusion that as we approach the "zero limit" of node reduction we're not so much talking about numbers in terms of structure features but more how the process advances in terms of voltage reduction at given frequencies compared to previous nodes as well as increases in transistor density. As such Intel is probably on the right track by simply giving names to future nodes indicating that lower numbers are "better."

Let's look at 10nm with Intel. Cannon topped out at 3.2GHz and most likely had terrible yields. Raptor Lake, which is still technically 10nm is now hitting 6GHz. Same "node" almost twice the frequency. That's better than any node shrink has ever achieved.
 
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I doubt that Raptor Lake Refresh (if any) would be on Intel 4. If it were, be prepared for disappointment since there might be clockspeed regression.
If they increase the internal caches (ALL OF THEM) and the various instruction buffers too, does that count as a refresh or a new architecture?
 

eek2121

Diamond Member
Aug 2, 2005
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Okay. This makes more sense. I think this Intel delay rumor was spurred by the rumor spread around last and this week that Apple is purchasing all of N3 for the next 2 years. I don't remember if they're still on N3, but I was wondering why this would be so if others were going to N3E. I've read some conflicting information on MTL-S but I think we all know it's not coming to desktop at this point and that may have been the plan all along. I get Intel wanting to push Arrowlake S on mobile only in 2025. They've still got mobile on lock but are facing stiff competition from AMD's new hardware. AMD however cannot provide as much raw product to manufacturing partners as Intel can. They can take a potential small beating or market loss there only to come roaring back with Arrowlake S. Though mobile MTL-S should provide them enough breathing room. Gelsinger stated MTL was a game changer. Whether this was a white faced lie or he really meant it is to be seen.

Again I doubt Arrow Lake cores, whatever form they take, will be on a non-Intel node. The GPU? yes. CPU cores will be on an Intel process, GPU on TSMC, and everything else? Depends on who is cheaper.

Moving to TSMC for a client core would be a disaster for Intel in many ways. So I firmly believe they won’t do it. Further, they have no reason to.

Just putting this here to stake my claim. We shall see how it plays out.
 
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A///

Diamond Member
Feb 24, 2017
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Again I doubt Arrow Lake cores, whatever form they take, will be on a non-Intel node. The GPU? yes. CPU cores will be on an Intel process, GPU on TSMC, and everything else? Depends on who is cheaper.

Moving to TSMC for a client core would be a disaster for Intel in many ways. So I firmly believe they won’t do it. Further, they have no reason to.

Just putting this here to stake my claim. We shall see how it plays out.
Who said that? I was drinking last night but I wasn't that far gone. What you say here is what some of us originally thought. The GPU makes more sense to be fabbed at TSMC because they excel at low power, relatively speaking. Intel's commitment was solidified earlier this week with the announcement of their next gen GPUs. Whether Koduri is still involved in the project is another matter and question.
 

Hulk

Diamond Member
Oct 9, 1999
4,375
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If they increase the internal caches (ALL OF THEM) and the various instruction buffers too, does that count as a refresh or a new architecture?

If you're talking about L1/L2/L3 then I think that would be a refresh. If you get into micro cache/reorder/branch order buffers, registers, loads/stores, and similar then I'd call it a "Tick."

New architecture generally involves increasing decoders and/or ports, which in turn requires the above structures to be increased/optimized to adequately feed the data.

Sometimes Intel would get things a little out of balance front vs. back end and fix it in later. For example, Haswell went from 6 to 8 execution ports but kept decoders the same. I'm sure Intel's models showed good IPC increases by opening up the back end. Then the front end became more of a bottleneck and they added a simple decoder with Skylake.

Then a return to the back end by going 8 to 10 ports with Sunny Cove. And finally with Golden Cove another simple decoder and 2 more execution ports were added. The buffers, registers, OoO order logic seems to be revised as the front/back end is opened up to support the greater data flow.

It *seems* like Intel rectified the bandwidth issues with Golden Cove by increasing L2/L3 with Raptor so Raptor Cove may be "balanced" and won't benefit from additional tweaking. But their models may have identified a few simple changes to allow for a few more percent IPC as well as some frequency increase.

But if we look back at all of the refreshes of Skylake because that's essentially what they were, all Intel did was add cores and increase frequency. Doubtful they will add cores (to the top of the stack) but I'm hoping they may be able to bring down power across the stack.

For example, while the 13900K can run 5.5GHz all cores, outside of a car radiator sized custom loop it just isn't sustainable with most of the silicon they are selling at 13900K from what I've been reading and experienced myself.

So let's assume the Raptor refresh can run 5.5GHz at the VID the "old" Raptor could run 5.1 or 5.2GHz. That would instantly be an upgrade for anyone moving from 13900K Raptor to Raptor refresh that doesn't have a monster cooling solution even though the label on the box would show the same specs!

Problem is how does Intel sell this? Right now for those of us in the "know" the 13900KS is more valuable for it's ability to run same clocks as 13900K but at lower voltages. No guarantee of course but you basically pay for a higher binned part. Intel "sells" this by slapping "6GHz" on the box. That number is meaningless outside of benches because other cores always drop that top number.

So in conclusion Intel is in a bit of a bind with this refresh. On the lower end parts below the 13900K/KS they can add some frequency across the board. But at the top of the stack there is really no where to go because they have that segment so finely binned with the 13900K and KS.

That's why I find this refresh interesting. I'm curious as to how Intel will proceed. And I hope Zen 5 is right around the corner and it is all we're hoping it is. Love seeing Intel's feet put to the fire and see how they respond. But AMD and Intel have pressured each other lately and both have responded to the pressure by making diamonds.
 
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moinmoin

Diamond Member
Jun 1, 2017
4,994
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Problem... or expected difficulty.
Still unexpected for Intel it seems. To me it has become completely ridiculous just how unprepared Intel repeatedly appears to be to every single delay that predictably comes. For all that Intel still fares surprisingly well in a way, but I'm not sure anymore what that whole (constantly overpromising and underdelivering, never on time) show's purpose is.
 
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Kocicak

Senior member
Jan 17, 2019
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But AMD and Intel have pressured each other lately and both have responded to the pressure by making diamonds.
These products are more race steam locomotives with their boilers close to explosion than diamonds.

The silicone pieces are fried and hundreds of watts of heat pumped through them. THEY SUFFER.

This is truly awfull.

Nothing calm, sparkly and diamondish about that.

This is diabolic fight with sulphur vapour pouring from under the heatspreaders.
 

LightningZ71

Golden Member
Mar 10, 2017
1,661
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If you're talking about L1/L2/L3 then I think that would be a refresh. If you get into micro cache/reorder/branch order buffers, registers, loads/stores, and similar then I'd call it a "Tick."

New architecture generally involves increasing decoders and/or ports, which in turn requires the above structures to be increased/optimized to adequately feed the data.

Sometimes Intel would get things a little out of balance front vs. back end and fix it in later. For example, Haswell went from 6 to 8 execution ports but kept decoders the same. I'm sure Intel's models showed good IPC increases by opening up the back end. Then the front end became more of a bottleneck and they added a simple decoder with Skylake.

Then a return to the back end by going 8 to 10 ports with Sunny Cove. And finally with Golden Cove another simple decoder and 2 more execution ports were added. The buffers, registers, OoO order logic seems to be revised as the front/back end is opened up to support the greater data flow.

It *seems* like Intel rectified the bandwidth issues with Golden Cove by increasing L2/L3 with Raptor so Raptor Cove may be "balanced" and won't benefit from additional tweaking. But their models may have identified a few simple changes to allow for a few more percent IPC as well as some frequency increase.

But if we look back at all of the refreshes of Skylake because that's essentially what they were, all Intel did was add cores and increase frequency. Doubtful they will add cores (to the top of the stack) but I'm hoping they may be able to bring down power across the stack.

For example, while the 13900K can run 5.5GHz all cores, outside of a car radiator sized custom loop it just isn't sustainable with most of the silicon they are selling at 13900K from what I've been reading and experienced myself.

So let's assume the Raptor refresh can run 5.5GHz at the VID the "old" Raptor could run 5.1 or 5.2GHz. That would instantly be an upgrade for anyone moving from 13900K Raptor to Raptor refresh that doesn't have a monster cooling solution even though the label on the box would show the same specs!

Problem is how does Intel sell this? Right now for those of us in the "know" the 13900KS is more valuable for it's ability to run same clocks as 13900K but at lower voltages. No guarantee of course but you basically pay for a higher binned part. Intel "sells" this by slapping "6GHz" on the box. That number is meaningless outside of benches because other cores always drop that top number.

So in conclusion Intel is in a bit of a bind with this refresh. On the lower end parts below the 13900K/KS they can add some frequency across the board. But at the top of the stack there is really no where to go because they have that segment so finely binned with the 13900K and KS.

That's why I find this refresh interesting. I'm curious as to how Intel will proceed. And I hope Zen 5 is right around the corner and it is all we're hoping it is. Love seeing Intel's feet put to the fire and see how they respond. But AMD and Intel have pressured each other lately and both have responded to the pressure by making diamonds.

Anything that touches any of the caches would be a significant floorplan revision and take a LOT of time to validate. Raptor Lake is already ASSUMED to be a "stopgap" product that was essentially a minimal changes upgrade to the Alder Lake dice. If Raptor Lake refresh is going to include expanded caches, it's going to take at least as long as Raptor Lake took to get to production, and I don't see Intel having that kind of lead time knowledge that Meteor and Arrow would be this far delayed. I believe that it is possible that they might increase the L3 cache size without touching core count. I believe that it is more likely that they just throw on another 8 e-cores and their included L3 to get from 36MB L3 to 42MB L3. The other possibility that their layout allows is, instead of throwing on another 8 E cores or 2 more P cores, they instead include two P-core sized segments of L3 cache instead, likely in between the P cores and the e cores. That could bring them north of 24+ MB of additional L3 to a product with 36Mb already. Assuming that they do the layout right, that could result in about 64MB of L3 for the upper end of the stack. How that would work for their own internal ring controls is completely beyond me, but, it doesn't seem impossible. It would absolutely bridge any gap that AMD gains from their 3dVcache products as Intel would likely retain their ability to clock as high as they do now on such a product.

That's still a LOT of silicon and investment for a refresh and it will certainly reduce dies per wafer yields for them. Maybe they have improved production volume enough to negate a lot of the extra cost there. Who knows...
 
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Hulk

Diamond Member
Oct 9, 1999
4,375
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These products are more race steam locomotives with their boilers close to explosion than diamonds.

The silicone pieces are fried and hundreds of watts of heat pumped through them. THEY SUFFER.

This is truly awfull.

Nothing calm, sparkly and diamondish about that.

This is diabolic fight with sulphur vapour pouring from under the heatspreaders.

What CPU do you use since they are all "truly awful?"

Or did you mean "awfull" as you spelled it meaning you are "full of awe" of these amazing CPU's? If so then I agree!

My point is that the AMD/Intel competition has been a great thing and the result has pushed both companies to produce the best CPU's on the planet at good price points. Without BOTH AMD and Intel the result would have been truly awful. The intense competition over the last 7 or so years has brought the best out of each company.

The pressure of competition has resulted in them UPPING their game, not cringing in defeat from the pressure.

For your edification the phrase "turning carbon into diamond" means that pressure brings out the best in an individual, team, or company.

This is what the competition has done for Intel and AMD. Whether or not you deem the products "diamonds" is not the point. The point is that is is without doubt the result of these companies competing with vigor!

Look at the leapfrogging and determine for yourself if the competition and pressure has led these companies to produce the best CPU's (metaphoric diamonds) possible for them at the time?
 

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Exist50

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Aug 18, 2016
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Who said that? I was drinking last night but I wasn't that far gone. What you say here is what some of us originally thought. The GPU makes more sense to be fabbed at TSMC because they excel at low power, relatively speaking. Intel's commitment was solidified earlier this week with the announcement of their next gen GPUs. Whether Koduri is still involved in the project is another matter and question.
 

Hulk

Diamond Member
Oct 9, 1999
4,375
2,252
136
I wrote that the amount of suffering chips are subjected to is awfulll.

Building up pressure in the boilers is not a good way to win a race.

Unless you are racing steamships or steam locomotive, or anything else steam powered.

But this is an honest disagreement. I know I operate better under pressure as do many people. Some people collapse under pressure. Point taken.
 
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Hitman928

Diamond Member
Apr 15, 2012
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Easiest thing would be that the 13900KS becomes the 14900K and then everything below gets less of an L3 cut than the current SKUs and/or a small frequency bump. That would make sense from a true refresh to me.
 
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Kocicak

Senior member
Jan 17, 2019
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I dont think that squeezing any more frequency from the current process and making 13900KS in bulk is possible.
 

Hitman928

Diamond Member
Apr 15, 2012
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I dont think that squeezing any more frequency from the current process and making 13900KS in bulk is possible.

Making a rebranded 13900KS in any more volume than current wouldn't be necessary and every SKU below that already have reduced clocks, so you would just reduce them less.

Edit: The probable exception would be the 14700k which would be more like a 13700K with more cache. This would create more separation between the 14700K and 14900K than exists between the current 13900K and 13900KS.
 
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coercitiv

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Jan 24, 2014
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You should have been able to OC Skylake to 4.8 at least.
Really?!
Out of the four samples, one engineering sample had 4.7 GHz at 1.4V two engineering samples achieved 4.6 GHz at ~1.4V and the one retail sample had 4.5 GHz at 1.275 volts before declocking when it was running at 4.6 GHz / 1.4 volts.

Intel's just basically eaten any OC headroom recently to win stock benchmarks.
 
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Exist50

Platinum Member
Aug 18, 2016
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Not just Pat the CEO saying the delay is bunk but Raichu here as well. Do wonder if ARL-S is planned to come out ASAP, like near Zen 5?
The timing is certainly going to be interesting. We know from an old leak that Intel originally planned to have Lion Cove + Skymont on N3 ready by end of this year, so really the question is what has slipped, and why.
 

A///

Diamond Member
Feb 24, 2017
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Was that to be taken at face value or that some part of the processor would be fabbed @ TSMC? Based on what limited info he probably had at the time I'm willing to let it slide. IDK who he is or if he's been correct in the past, but I wouldn't expect someone to know intricate details about the part of a multi chip processor months in advance of others.
 

A///

Diamond Member
Feb 24, 2017
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The timing is certainly going to be interesting. We know from an old leak that Intel originally planned to have Lion Cove + Skymont on N3 ready by end of this year, so really the question is what has slipped, and why.
Consolidated? I don't remember Lion Cove taping but I also don't pay attention to online discussion forums much.
 
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