QS will be the important one though. As well as what the overall binning looks like.
What does "QS" stand for again?
Also we really have no idea what "Intel 4" means in terms of feature size. Intel 7 is based off of 10nm, which itself became a nebulous measurement many nodes ago. Intel 4 could really just be a minor improvement to Intel 7. Too bad we never get to know transistor density anymore because that would provide more information than these fictitious node names.
Intel actually increased Transfer Gate Pitch with Coffee Lake with 14++ to increase clocks (and leakage) at the expense of die area (density) and idle power (from Anandtech). See chart below.
My point is that Intel really only needs to tweak Intel 7 for slightly better density and efficiency (power) to call it Intel 4. None of this relates to actual numbers anymore. The only indication we have of how a process is really "working" is how many cores do they fit on it and what is the throughput of those cores. If they are squeezing more, higher IPC cores, or even the same number of higher IPC cores then density is increasing. Intel used to love touting those numbers or at least density increases. Not so much now with TMSC around.
So playing by the new rules, Intel could have called 14+++ Intel 12 or something like that, and then 14+++++ Intel 10, etc... This tend hide process delays. They kind of did that with Intel 7, still really 10nm but deemed to be "Intel 7." The bottom line is getting rid of the + system is a good marketing idea as Intel 7, Intel 4, Intel 20A, Intel 18A, are just representations of density/iso frequency decreasing. The probably should have created finer graduations, Intel 7, Intel 6, Intel 5, like TMSC does to create the impression that they are really cranking along with these process shrinks!
Instead we consider the last process at 14nm the "true" 14nm. Same with 10nm except now that will be Intel 7. So we really have Tiger Lake ending 10nm and RPL R closing the door on Intel 7. So it doesn't "feel" like 10nm+++++++++++++++++.
Minimum Feature Size | Based on measurements of the die, out of the 26mm2 increase from Kaby Lake 4 core, 91.5% is for CPU area, and the rest likely accounting for the change in gate pitch across the whole processor. | | | |
| 22nm | 14/14+ | 14++ | |
Transistor Fin Pitch | 60 | 42 | 42 | |
Transistor Gate Pitch | 90 | 70 | 84 | |
Interconnect Pitch | 80 | 52 | 52 | |
Transistor Fin Height | 34 | 42 | 42 | |