I would say Conroe, Nehalem and Haswell.
It is my opinion that the Big/Little approach is more relevant today than simply making all cores the same.
Single thread and multithread compute are different animals.
Assume due to economic constraints you have a given die area to produce a part.
If you were to design the part to ONLY run MT applications, and perfectly scaling ones at that (think Cinebench) then you would cram as many E cores onto the chip as possible because they are more area efficient for MT than P cores. Let me back up that claim.
1 P at 6GHz would do about 3000 points CB R23 while an E core cluster at 4.3GHz would do about 4500 CB R23 points. Truth be told 1P is not as large as an E cluster, but the E cluster is not 50% larger as is indicated by the performance increase of the E cluster. It's more like 27% larger. Also MT P's at 6GHz is kind of unrealistic but the point is for pure MT performance die area is best filled with E cores for maximum performance.
Now if you strictly need ST performance you'd want 1 giant super fast P core. Or maybe 4 or 5 just to be sure you had enough of them. Maybe you'd even want 8 just to be "safe!"
So now if you want a part that is good at both ST and MT you'd want enough P's to handle your ST applications and then a bunch of E clusters to increase MT performance.
So why didn't AMD do it first? Probably because with their process advantage they didn't need to deal with the additional design and fabrication complications and cost. They were already in the lead performance-wise. Intel on the other hand didn't have the luxury of the TMSC nodes and needed to figure out a way to compete on a less advanced node and they did it. If AMD had gone to hybrid with Zen 4 they would have smashed Alder Lake and Raptor Lake.
The point is moving forward as more and more applications become increasingly multithreaded the hybrid approach will make more and more sense.