Anantech speculated that it had 12 LLC/Ring Stops because when Intel Disabled one of the quad cluster in the 12700k the CPU lost 5 MiB of L2 Capacity instead of losing just 3
Sorry, I meant 5 MiB L3 Capacity was lost by disabling one of the cluster.Little to do with technical details and more to do with positioning. 12900K is an i9. 12700K is an i7. Since quads of E cores all share one L2 cache it doesn't make sense it's more than one stop.
What I hear you say is 3nm vcache for zen5 is already in production.Cache is the simplest product to validate on a new process. Just seems natural to scale cache products up to justify getting a process out the door at the earliest stage. Starts your path to the black a bit sooner than conventional development models.
That's a gross misrepresentation of what I actually said. My previous post contained only facts:I'm clearly wasting my time responding, but as covered here several times over, TSMC never once publicly promised that N3 would be on the same schedule as N5, and the current timeline is perfect in keeping with what they have said.
The changed Meteor Lake plans (its delay and seemingly even backport of the GPU tile from N3 to N4/5) further supports the N3 delay observation.
The moment, when basic mathematics lose its validity and reality+basic logic kicks in.You are essentially stacking two sets of rumors with this one, to claim something has gone wrong.
Two wrongs (or Rumors) don't make a right.
Intel has said there are no Meteor Lake delays, so you really can't use rumors claiming that as some kind of "fact" that proves something going wrong behind the scenes.
The key that you are leaving out is any shred of evidence that Meteor Lake was ever using N3. Care to share that? The closest thing that we have to being official from Intel is that the N3 orders in your link were for Arrow Lake pre-production chips (engineering samples and the like). Even your link says it isn't clear what chips would use N3.The changed Meteor Lake plans (its delay and seemingly even backport of the GPU tile from N3 to N4/5) further supports the N3 delay observation.
That's a gross misrepresentation of what I actually said. My previous post contained only facts:
*TSMC announced N3 in 2020 for H2'22 HVM
*However, in 2021 during a Q&A TSMC more precisely specified its schedule as Q3'22
*This has since shifted to (late) Q4'22
Hence, the statement that TSMC is "[perfectly] keeping with what they have said" is wrong.
The changed Meteor Lake plans (its delay and seemingly even backport of the GPU tile from N3 to N4/5) further supports the N3 delay observation.
So, if I'm understanding the results properly: The new Xeon, with a roughly 25% core advantage, a 10% clock speed advantage, almost double the cache, larger L2 and likely a better memory subsystem only managed to get roughly 10% more "GOPS"?I Was able to find this Jewell... A Release Sample of the Xeon Platinum 8470 On a 2S system(104C/208T Total) On SiSoftware Official Benchmark Ranker, I am surprised that Wccftech have not posted yet.
View attachment 65657
It's a performance improvement over the previous 8380 Ice Lake
View attachment 65660
The Ice Lake Xeons were boosting 45% Higher on the benchmark(2S System), The Average Speed Efficiency on the Sapphire Rapids much higher.So, if I'm understanding the results properly: The new Xeon, with a roughly 25% core advantage, a 10% clock speed advantage, almost double the cache, larger L2 and likely a better memory subsystem only managed to get roughly 10% more "GOPS"?
I'm not very impressed... I hope this is still not running it's "final production tune".
If I'm reading that correctly, isn't that aboost in FP but a regression in integer?I Was able to find this Jewell... A Release Sample of the Xeon Platinum 8470 On a 2S system(104C/208T Total) On SiSoftware Official Benchmark Ranker, I am surprised that Wccftech have not posted yet.
View attachment 65657
It's a performance improvement over the previous 8380 Ice Lake
View attachment 65660
The key that you are leaving out is any shred of evidence that Meteor Lake was ever using N3. Care to share that? The closest thing that we have to being official from Intel is that the N3 orders in your link were for Arrow Lake pre-production chips (engineering samples and the like). Even your link says it isn't clear what chips would use N3.
Intel has said there are no Meteor Lake delays, so you really can't use rumors claiming that as some kind of "fact" that proves something going wrong behind the scenes.
Intel only really said that products would be in stores in 2023. You can see why they wouldn't want to use N3 for the IGP if Meteor Lake is going to end up being mostly Celerons.
As it currently stands, Intel may well be the only x86 vendor to ship sub 5nm CPUs in 2023.
AMD has not exactly been an early adopter of TSMC's processes, so I doubt many were expecting N3 CPUs from them in 2023 regardless of whether they started N3 mass production in Q3 or Q4 of this year.
While it is dated 27 July, wasn't the 5995wx out by then ? Thats only 2 weeks ago. They say in the notes "the latest tech" but the 5995wx easily beats the 3990wx. And the 3990wx for the most part beats the new X9 HEDT. The 5995wx could be a slaughter. (as way less wattage( 280 vs 500)I found another Jewel(albeit an early ES sample)
Intel Xeon W9 HEDT Sapphire Rapids Preview & Benchmarks
Intel Xeon W9 HEDT Sapphire Rapids Preview & Benchmarks – SiSoftware
www.sisoftware.co.uk
Look at your statement. It is clearly not production performance.So, if I'm understanding the results properly: The new Xeon, with a roughly 25% core advantage, a 10% clock speed advantage, almost double the cache, larger L2 and likely a better memory subsystem only managed to get roughly 10% more "GOPS"?
I'm not very impressed... I hope this is still not running it's "final production tune".
Look at your statement. It is clearly not production performance.
Yes, but it has not been tested on the Sisoft Benchmark.While it is dated 27 July, wasn't the 5995wx out by then?
I think it is quite likely AMD is skipping N3 and jumping straight to N3E.
N3E timing is ~ H2 2023 production, which may align quite well with Zen 5 launch. TSMC said that they have a lot of "customer engagement" for that node, so it may include AMD, which is going to be 2nd largest customer of TSMC.
N3E looks to be lining up perfectly for Apple for next year's iPhone, so there aren't going to be very many wafers left over for others until late in the year. They always say they have a lot of "customer engagement" but that doesn't mean a lot of customers who will be taking large numbers of early production wafers.