But wait! Where is RWC+ Gelsinger promised us?
Looks like RWC+ isn't showing up, or is either such a minor update that it's not significant.
Probably. Seems to basically just be RWC on Intel 3. Maybe they'll make a few tweaks, but if they didn't even bother to give it a new name like they did Raptor Cove, can't expect much.Looks like RWC+ isn't showing up, or is either such a minor update that it's not significant.
Probably. Seems to basically just be RWC on Intel 3. Maybe they'll make a few tweaks, but if they didn't even bother to give it a new name like they did Raptor Cove, can't expect much.
I mean, if they changed it much, surely they would have given it a different name, right? Raptor Cove has next to no architectural changes, and they still gave it one. Seems like they're still following the naming convention of tying the core name to process. Related, but, what's the Atom core labeled in this Sierra Forest leak? SGL?2021 with the new node naming and announcement of IDM 2.0 and 20A process that Granite Rapids was put as Intel 4.
2022 was when Granite Rapids was moved to Intel 3. Are you sure about what you are saying, that they did not change the core? Since that's a 2021 slide?
I mean, if they changed it much, surely they would have given it a different name, right? Raptor Cove has next to no architectural changes, and they still gave it one. Seems like they're still following the naming convention of tying the core name to process. Related, but, what's the Atom core labeled in this Sierra Forest leak? SGL?
Skymont was always an Atom core name. Though that should be a particularly fun one.And they did that for Skymont. Rumor mills had it as a successor for a Core chip, not Atom/E core based.
Yeah, it seems reasonable enough. Even from just a die size perspective, it's around what you'd expect from 2-3 large compute dies.Also, do you think the 80 core thing is current? Because 80 core = SP, 120 core = AP is exactly what MLID said(I don't watch his full video either. I just skip to the written part).
I'm increasingly convinced that at some point, Intel wanted to move GNR to Lion Cove. It would make sense for them to want to use their latest core. But the delay of Arrow Lake into 2024 makes me wonder if Lion Cove itself is not having schedule issues. And there's one detail that would be hard to reconcile.If the change is minimal then it would stand to reason the time when Pat claimed it was changed, either he was lying or they had a second Intel 3 core going.
Chiplets are the future.. you get spectacular scalling with them 😉💻View attachment 78646
Oh wow the slides keep on looking better and better
So that is why AMD is blowing Intel away right now....Nice of you to point out that AMD is the future, and the future is now for them !Chiplets are the future.. you get spectacular scalling with them 😉💻
this is top tier trolling rnSo that is why AMD is blowing Intel away right now....Nice of you to point out that AMD is the future, and the future is now for them !
true, but people like Jenson, Steve Jobs and Lisa are one of a kind CEOs. These people know where the industry is heading.
One look at the ARC team and you know its headed for nowhere. They spent months getting DX9 to work properly and the most popular DX9 game CSGO is now getting replaced with CS2 which is vulkan based. CSGO will no longer exist.
I bet you a whole cheese island that Nvidia knew CS2 was coming(After all it was leaked via Nvidia channels). Intel spent hyping up DX9 benchmarks with CSGO as being the primary example, later in 2023 Summer that will will no longer exist.
That is just one example.
No leaks of diamond rapids ?Given how accurate the GNR mockup was on Intel's presentation, I also have to wonder if DMR is actually going to end up like this:
View attachment 78661
TBH, I expect one of the next EPYC to look a bit like this.Given how accurate the GNR mockup was on Intel's presentation, I also have to wonder if DMR is actually going to end up like this:
View attachment 78661
What are those files for/from? Server RWC will obviously have the AVX512 and AMX support we see in GLC server vs client, but the core uarch should be functionally identical.It is a different core.
View attachment 78655
The total area is exactly the on-package-area that a full blown Genoa occupies (so that caps and stuff still get the same space as now). Die area numbers are just exactly Genoa and will surely change. Geometries were modified in order to fit everything and get enough beachfront (not sure about the split IOD connection though).
Have fun dismissing this armchair engineer's work 😉
tl;dr: There is no universal chiplet tax - just different physical Interconnect implementations.Can AMD fit 16 chiplets? That's for sure, but the chiplet power tax will be there. Right now they can easily afford, just like they were able to afford it with 8 chiplet zen2/3 products.
But it has its power price, Zen2 era chiplets were like 16-25w a piece in fully loaded chip and IOD was 100w+ monster.
What happens IF Intel closes process gap and has MCs on compute dies? Despite naming, nothing in Infinity fabric is infinite and they chew power.
There is nothing superior about what Intel is doing or will be doing in the short term about their DC tile strategy. They seem to have lost focus of what really matters.
AMD is playing the same card since Zen2 and is riding TSMC process advantage. I think their real current innovation and advantage in packaging is 3D cache. Very substantial one.
As customer i don't care how much Intel or AMD pay for their silicon, i leave that to their beancounters. As long as they both sell competitive chips for right price they can go for each others throat, i don't care.
Everything for Intel rides on their ability to fix process issues and ability to execute on roadmap. We already see the signs of AMD reacting in "hybrid" core introduction and hopefully You are right that they will rework IO part. But as long as MC is away from compute die and L3 is sharded they will continue to pay power/perf taxes.
The "my workload does not communicate between threads much" part of AMDs "lets increase count of chiplets" business advantage dissapears when Intel introduces their own "Atom" driven horde of cores.
Can AMD fit 16 chiplets? That's for sure, but the chiplet power tax will be there. Right now they can easily afford, just like they were able to afford it with 8 chiplet zen2/3 products.
But it has its power price, Zen2 era chiplets were like 16-25w a piece in fully loaded chip and IOD was 100w+ monster.
What happens IF Intel closes process gap and has MCs on compute dies? Despite naming, nothing in Infinity fabric is infinite and they chew power.