Wouldn't vertically stacking chiplets cause the final package to be extremely thick ? This would mean that such a processor can't be used in a small form factor like laptops or phones.
They thin the wafers before stacking, so a dozen chips stacked on top of each other wouldn't even add 1mm in height to the package. I think heat is a bigger issue, since you concentrate more transistors in a given area. If before you had a big chip of x transistors in 600 mm^2 but now you have that many transistors in a stacked chip in 150 mm^2, you have to move 4x the heat per mm^2.
Backside power delivery (which is still a ways out) will make this easier than the current method which is organized as a "grid" of a given pitch specific to a given process.