I don't think their packaging tech as is is failing them. Regardless of how good your packaging tech is, putting together 63 parts/47 chiplets can't be cheap nor have an excellent yield. They essentially made this design because they could and likely needed to hit a target not achievable otherwise, not because it's an economical and smart design (similarly to how I consider the mirrored chiplets of SPR as inane, not smart).Do we have any solid info on how their packaging tech is failing them in this instance?
I don't think their packaging tech as is is failing them. Regardless of how good your packaging tech is, putting together 63 parts/47 chiplets can't be cheap nor have an excellent yield. They essentially made this design because they could and likely needed to hit a target not achievable otherwise
Well, you know the old saying, "if a little is good then more must be better". Right, right?I don't think their packaging tech as is is failing them. Regardless of how good your packaging tech is, putting together 63 parts/47 chiplets can't be cheap nor have an excellent yield. They essentially made this design because they could and likely needed to hit a target not achievable otherwise, not because it's an economical and smart design (similarly to how I consider the mirrored chiplets of SPR as inane, not smart).
I don't think their packaging tech as is is failing them.
A350M is better performing than I expected. Yes it's late but it should allow them to get a foothold in the market.
But that's the thing: That's not related to packaging tech "underperforming" or some such, that's down to imo nutty design decisions. As @IntelUser2000 said they wanted monolith like latencies at all cost and that's how they paid for it, with plenty silicon area (and for whatever reason with little investment into area optimization as there seems to be plenty dark silicon).Hmm. Well I was sort of thinking, if you look at how much silicon is expended on EMIB on Sapphire Rapids, that's one instance of packaging tech underperforming vs. expectations. Or at least my expectations. I didn't think Intel would need that much area just to bind four (admittedly large) chiplets together. My ideas about what those silicon bridges would be like were completely off, at least with respect to Sapphire Rapids.
But that's the thing: That's not related to packaging tech "underperforming" or some such, that's down to imo nutty design decisions. As @IntelUser2000 said they wanted monolith like latencies at all cost and that's how they paid for it, with plenty silicon area (and for whatever reason with little investment into area optimization as there seems to be plenty dark silicon).
moinmoin said:said they wanted monolith like latencies at all cost and that's how they paid for it, with plenty silicon area (and for whatever reason with little investment into area optimization as there seems to be plenty dark silicon).
@jpiniero Not according to the Time Spy results. They are roughly even on the Default mode, and A350M is quite a bit faster on Performance.
Makes one wonder what they did in all the time while they waited for the roadblock to be removed. Optimizing designs to not require mirrored dies and remove all unnecessary areas wasted by dark silicon could have been done while development on the process node held them back. As is many Intel designs lately seem very half baked and oddly rushed, despite being late.The only issue is that Sapphire Rapids is late, very late.
They have to be scrapping some ambitious design late in the game and turning to plan B. What else could explain these delays, other than sheer laziness and/or incompetence?As is many Intel designs lately seem very half baked and oddly hurried, despite being late.
They have to be scrapping some ambitious design late in the game and turning to plan B. What else could explain these delays, other than sheer laziness and/or incompetence?
As is many Intel designs lately seem very half baked and oddly rushed, despite being late.
So far we assumed state of the process node was/is Intel's only issue. Design should be independent from that. Apparently design continuously had/has serious issues as well, and unlike with improving node yields designs stayed the rushed way until the end?That's what being late means though. You don't delay to make it better, it's delayed because it has issues that needs to be resolved.
Like Moore's law, they should name this the Krzanich HangoverThe problems date back to incompetent management in the Kraznich days, simple as that, and because development cycles in total are pretty long, they are still suffering the after effects from it.
So far we assumed state of the process node was/is Intel's only issue. Design should be independent from that. Apparently design continuously had/has serious issues as well, and unlike with improving node yields designs stayed the rushed way until the end?
So far we assumed state of the process node was/is Intel's only issue. Design should be independent from that. Apparently design continuously had/has serious issues as well, and unlike with improving node yields designs stayed the rushed way until the end?
While I agree with you in general, note that we are talking about basic stuff done early while planning the design:I don't think you can separate designs completely from process. If you look at all performance metrics(performance and performance per watt), a new process design is just better all the way around.
So design would be affected by process delays, because now the design team is unsure of what's happening. Look at why the Tick/Tock methodology came about. The design team needs to know the parameters of the process. The process is the foundation.
It would have rather turned out better if they just said "14nm will be cutting edge for 4 years" rather than promising "10nm will be next year" every year.
That's why designs like Goldmont Plus turned out really good since Atoms were purposely on an older process anyway, so they were much less subject to process delays.
The only way I can see the current product as the result of a halfway sane development process is that the decision to split up SPR into four chiplets itself was done late in development, essentially splitting up an existing huge design that through some existing symmetry allowed to reuse two of the four cuts, one of them achievable through mirroring, and simply stick to it the areas required for EMIB to put the cuts back together. But that'd be a whole other category of a rush job.
3dmark, etc isn't a true reflection of actual gaming performance. AMD's slide is more realistic.
Performance in Cyberpunk 2077 and Horizon Zero Dawn is respectable. I hate that reviewer for not testing raytracing.Back to topic: ARC benchmarked against GTX 1650 Mobile. The 1650 is about 20% faster.
Performance in Cyberpunk 2077 and Horizon Zero Dawn is respectable. I hate that reviewer for not testing raytracing.
Source for the A350M scores?The Default mode for the A350M got 2400 points which is only 5-10% better than 680M. At the higher power Performance mode it gets 3100.
Source for the A350M scores?
Back to topic: ARC benchmarked against GTX 1650 Mobile. The 1650 is about 20% faster.