mrob27
Member
Have a look at the memory controllers bellow the L3 Cache, the empty space is smaller than IvyBridge GT2 (HD4000) from the pic above, that only makes the die much smaller and thus not GT3 but probably GT1.
About that empty space in Ivy Bridge: Refer to the Ivy Bridge die sizes article again.
The "biggest" Ivy Bridge is the HE-4, 8.141 x 19.361 mm and has 8MB of cache. The Ivy Bridge HM-4 still has 4 cores, but only 6MB of cache, and is only 7.656 mm wide, about 1/2 millimeter smaller. Clearly they slice a bit out of each piece of L3 cache, which makes the chip narrower. It also has GT1 graphics, so as this post suggested, the GPU gets a lot smaller. For the dual-core H-2 and M-2 variants, the empty space is used to accommodate the dual-channel memory controller.
I don't completely agree with the photos in that post, clearly IntelUser2000 cut the L3 cache section in half, when actually it needs to be cut by 25%. If you look at the Sandy Bridge image from AtenRa's post:
You can see pretty easily the "dead space" underneath the ring bus stop in each of the four L3 cache slices, and that dead space is exactly 1/4 the height of the cache section. For Ivy it's similar, most easily seen in this image from Intel Sweden:
But the rest of IntelUser2000's analysis is pretty accurate and he predicted the die sizes pretty well.
Anyway...
...for Haswell it's a different game. They'll definitely cut the die in different ways and use different layouts, but suppose they might have a variant with less cache and the same GPU? Then they could use that "dead space" to accommodate the GPU.
I believe that in the maybe-Haswell-wafer image we're discussing, the GPU occupies the full width of the die, and that's why the visible dead space is so small.
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