zephyrprime
Diamond Member
- Feb 18, 2001
- 7,512
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Hey, I already started a thread about this topic in the CPU group. Anyway, there's been quite a bit of discussion about this issue for the last few days.
Some have pointed out that the current P4 has a 28 stage pipeline if you include the stages before the trace cache and after the point where branches are determined.
Others have pointed out that Intel supposedly did some calculations some years back that showed that the theoretical optimal pipeline length is 40 stages.
Some have pointed out that the current P4 has a 28 stage pipeline if you include the stages before the trace cache and after the point where branches are determined.
Others have pointed out that Intel supposedly did some calculations some years back that showed that the theoretical optimal pipeline length is 40 stages.
I don't think there's really a lot that needs to be done to optimize compilers for prescott that isn't already done for the P4. Really, you can only avoid branching to a certain degree.With the P4, they could seed compilers with information on how to handle the longer pipeline, and more importantly, how to handle SSE2. Prescott however has just the longer pipeline, so there's a decent chance Intel won't be able to get back as much effeciency out of the Prescott, since the only thing going for it this time are more pipeline compiler optimizations