Intel Investor Meeting 2014

[witeken]

16FF+ is the same density as 16FF; it's just 15% faster. I know you participated in this discussion previously... you must have forgotten, or missed the conclusion.

In any case, I was referring to a node that didn't have the same density (-> higher density) as 20nm.

 

[witeken]

So Bay Trail is expected to power budget laptops and desktops, while Cherry Trail goes into tablets?

Remember, Bay Trail-M will not be followed up by Cherry Trail, but by Braswell. Not sure if there are any differences except for the name.

 

[kimmel]

Remember, Bay Trail-M will not be followed up by Cherry Trail, but by Braswell. Not sure if there are any differences except for the name.

The main differences are the interfaces available... eg: pcie ports.

 

[witeken]

+1

(and I don't do that very often )

9 thanks, if I counted correctly

Glad you enjoyed it, hopefully as much as I enjoyed watching the presentations .

One thing that I have missed because stopped watching is the SSD presentation (videos will be available soon, presentation already available: http://intelstudios.edgesuite.net/im/2014/live_im.html). The big news there was the use of 3D NAND in 2015. Intel says it will be very good (of course..). It should allow for 10TB SSDs in the coming years. This means that costs will continue to go down at a nice rate and HDDs will basically become obsolete. HDDs were good for lots of cheap storage, but a lack of innovation will now kill that market.

To conclude the IM, I think it's fair to say that Intel has shown that they're still extremely innovative and they have a great pipeline and attitude. However, that doesn't mean time (to market) is on their side. As they opened the presentation, it will cost them money, and I do think they should still be a little bit ashamed that they're still having to report delays.

2015 should be good year with the widespread release of 14nm from top to bottom (except smartphones) with Broadwell and Skylake, Xeon Phi but not Broadwell-E. Contra-revenue will disappear, 10nm will be prepared, wires will be removed, graphics will be enhanced, the NUC will shrink to USB form factor and 3D RealSense deployed.

And as the icing on the cake, Moore's Law's 50 year anniversary will be celebrated; we can only wonder how.

 

[NTMBK]

Remember, Bay Trail-M will not be followed up by Cherry Trail, but by Braswell. Not sure if there are any differences except for the name.

It may be that Braswell adds dual-channel memory support and more PCIe lanes. (Just a guess.)

 

[mikk]

Did anyone ask about their use of Imagination GPUs in the future? Intel seem to be trying to improve reuse of their IP (Bay Trail forming basis of KL cores, GenX graphics in both Core and Atom, obviously Haswell cores being used from tablets up to 140W servers), and replacing licensed GPUs in mobile parts with their own tech seems like the next step.

Intel is using their own GPU technology starting with Gen9 from Skylake to Smartphones in the future.

It may be that Braswell adds dual-channel memory support and more PCIe lanes. (Just a guess.)

Bay Trail already is dual-channel. Braswell is a renamed Cherry View.

 

[NTMBK]

Bay Trail already is dual-channel. Braswell is a renamed Cherry View.

Sorry, I meant Braswell/Cherry View vs Cherry Trail. (I thought it was only Bay Trail M that has dual channel? Might be wrong though.)

 

[kimmel]

3d nand slide:

Is Samsung currently shipping 32 layer?
http://www.samsung.com/global/business/semiconductor/html/product/flash-solution/vnand/overview.html

Stacking the vertical layers in three dimensions allowed for 24-layer products in 2013 and has increased to 32-layer products in June of 2014. Using stacking instead of photolithography to increase capacity eliminated the patterning limitation.

Edit: Well then...
http://techreport.com/news/27397/intel-3d-nand-has-32-layers-and-256gb-per-die

Samsung's 32-layer V-NAND has 86Gb per die in MLC mode and 128Gb in a TLC config, giving Intel and Micron a substantial density advantage—at least per die. That said, a new generation of V-NAND should be ready by the second half of 2015. It will be interesting to see how those chips stack up against the 256Gb monsters Intel has cooked up with Micron.

 

[ShintaiDK]

10TB SSDs within a couple of years. Looks nice.

 

[witeken]

Intel17 has been absent from this thread so far, interestingly enough. I wonder what he thought of the IM.

 

[Fjodor2001]

10TB SSDs within a couple of years. Looks nice.

Yes, but at what price? We already have 8 TB SSDs by the way, if you're willing to pay for it:

http://www.tweaktown.com/news/40935/memblaze-debuts-new-8tb-nvme-eblaze4-pcie-ssd/index.html

 

[witeken]

Yes, but at what price? We already have 8 TB SSDs by the way, if you're willing to pay for it:

http://www.tweaktown.com/news/40935/memblaze-debuts-new-8tb-nvme-eblaze4-pcie-ssd/index.html

They obviously mean in the mainstream line-up. Today you have 64GB to 512-1024GB. 3D will enable those offerings to extend to >10TB; a 10-20 decrease in price/bit. That's the whole supposed beauty of 3D NAND. Imagine if Moore's Law were 3D instead of 3D, then each generation you'd get a 3X increase in transistors. 3D NAND is a bit like that.

Edit: I'm watching the presentation, and he specifically refers to Diane's [datacenter] business, so I'm not sure if those are intended for the consumer market.

 

[jpiniero]

They obviously mean in the mainstream line-up. Today you have 64GB to 512-1024GB. 3D will enable those offerings to extend to >10TB; a 10-20 decrease in price/bit. That's the whole supposed beauty of 3D NAND. Imagine if Moore's Law were 3D instead of 3D, then each generation you'd get a 3X increase in transistors. 3D NAND is a bit like that.

Well, if you think about it, FinFet is really 2.5D so 3D isn't a stretch for a CPU. The heat density would be killer though.

 

[Fjodor2001]

They obviously mean in the mainstream line-up. Today you have 64GB to 512-1024GB. 3D will enable those offerings to extend to >10TB; a 10-20 decrease in price/bit. That's the whole supposed beauty of 3D NAND. Imagine if Moore's Law were 3D instead of 3D, then each generation you'd get a 3X increase in transistors. 3D NAND is a bit like that.

Edit: I'm watching the presentation, and he specifically refers to Diane's [datacenter] business, so I'm not sure if those are intended for the consumer market.

Samsung is already shipping 32 layer 3D V-NAND chips. According to kimmel's post, Intel's corresponding chips will only have 2x higher capacity (256 Gb compared to 128Gb for Samsung). So why aren't we seeing mainstream 5 TB SSDs already on the market if your logic holds true?

 

[witeken]

Samsung is already shipping 32 layer 3D V-NAND chips. According to kimmel's post, Intel's corresponding chips will only have 2x higher capacity (256 Gb compared to 128Gb for Samsung). So why aren't we seeing mainstream 5 TB SSDs already on the market if your logic holds true?

So with "your logic" I guess you assume that it will drive costs down. I don't really expect any significant bumps, just a continuation of the current trend. Intel's 3D NAND will be 256Gbit, up from the current 128Gbit used by both planar and Samsung's 3D technology. Increasing the number of bits per die is obviously very important to scale costs down. NAND doesn't really scale well below ~16nm, so this is a logical thing to do.

As the 3D technology moves forward, they will obviously reach those 5-10TB chips some time, and according to Intel reasonably soon.

 

[ShintaiDK]

Its wrong to call it Intels NAND. It is IMFT. Intel and Micron partnership.

Information is just released at Intels investor meeting.

Samsung got 86Gbit MLC and 128Gbit TLC.
IMFT got 256Gbit MLC and 384Gbit TLC.

Both using 32 layer.

SK Hynix will also join the 3D club within a month or 2..

 

[III-V]

Samsung is already shipping 32 layer 3D V-NAND chips. According to kimmel's post, Intel's corresponding chips will only have 2x higher capacity (256 Gb compared to 128Gb for Samsung). So why aren't we seeing mainstream 5 TB SSDs already on the market if your logic holds true?

Well, there's the issue of how much memory the controller can address. No consumer SSDs can address that much.

But I don't think 5TB, and certainly not 10TB, will be mainstream by any means. This is a doubling of capacity per die compared to what they're already shipping. It does appear to be significantly cheaper than Samsung, though, looking at kimmel's post with Samsung's die capacities. I'd imagine the $/GB has improved much more than 2x.

I'd imagine Intel and Micron didn't regress nodes with their 3D NAND, unlike Samsung that's using something in the 40nm range.

 

[kimmel]

Speculating about future prices and future exact shipping densities isn't exactly productive. I just love the die cross sections shots. Crazy that they (Samsung and Intel) can make that yield.

When will we see 3d stacked transistors in logic? That will be an interesting day.

 

[meloz]

Its wrong to call it Intels NAND. It is IMFT. Intel and Micron partnership.

Information is just released at Intels investor meeting.

Samsung got 86Gbit MLC and 128Gbit TLC.
IMFT got 256Gbit MLC and 384Gbit TLC.

Both using 32 layer.

SK Hynix will also join the 3D club within a month or 2..

Do you have any information about what Toshiba are planning? Will they be licensing IP from SK Hynix or are they developing their own? Their acquisition of Indilinx (via OCZ) seems to suggest they are pretty serious about SSD market as well.

In future I see only three SSD players: Intel (+Micron), Samsung and (maybe) Toshiba.

 

[Idontcare]

Speculating about future prices and future exact shipping densities isn't exactly productive. I just love the die cross sections shots. Crazy that they (Samsung and Intel) can make that yield.

Not that crazy in reality, with redundancy they basically seal off areas of the chip that are affected by particles or process-induced issues and still use nearly every single chip on the wafer.

Yield losses are basically going to be down to a defect in the minimally present controller logic, and hitting parametrics (binning).

The real challenge in going 3D is dealing with cost. As a manufacturer, your cost structure increases (not decreases) as you add more layers and make the chip have higher and higher effective bit density.

It is reversing Moore's Law. A wafer that needs 32 layers versus one that needs 16 layers of bit cells is going to cost more to manufacture because it will spend more time in the fab.

Physically shrinking the cells, and packing more them into a square area (not a cubic volume) is the only thing that is going to reduce manufacturing cost per bit (which is what Moore's Law is all about).

When will we see 3d stacked transistors in logic? That will be an interesting day.

Unlike stacked capacitors or floating gates for memory ICs, logic chips need a well formed crystalline channel in order for the xtors to hit the required mobility (hole or electron) in order for the gate delay to be as low as it needs to be for commercial viability.

Right now there is no technology for creating layers of perfectly well-formed channel material (be it silicon, SiGe, or III-V material) beyond the methods used to create boules of silicon nowadays (then turned into wafers).

Epitaxial deposition works, but it requires a underlying well-formed (perfect) crystalline lattice from which to build upon, and that condition simply doesn't exist once you've deposited and processed the materials necessary to make the first layer of transistors on a logic device.

That is why the industry is instead trying to make TSV (through silicon via) work. But again, that goes in the opposite direction of Moore's Law. Going 3D increases cost, not decreases.

 

[witeken]

One interesting detail that I noticed is Intel's projection of 10nm (= foundry's 2nd gen FF) HVM.

They project it at mid-2017. Also note the absence of projections for their own 10nm. They seem to know better what the competition will do than themselves! They don't want influence TSMC and Samsung, do they?

And for those who have not seen it, another great slide from Intel about consolidation (page 60): http://intelstudios.edgesuite.net/im/2014/pdf/2014_Intel_IM_Smith.pdf

 

[Fjodor2001]

It is reversing Moore's Law. A wafer that needs 32 layers versus one that needs 16 layers of bit cells is going to cost more to manufacture because it will spend more time in the fab.

Physically shrinking the cells, and packing more them into a square area (not a cubic volume) is the only thing that is going to reduce manufacturing cost per bit (which is what Moore's Law is all about).

32 layers will spend more time in the factory than 16 layers. But will the total time in factory still not be less for one 32 layer chip than two 16 layer chips?

I imagine there must be certain manufacturing steps that are "fixed overhead" regardless of the number of layers.

 

[SAAA]

32 layers will spend more time in the factory than 16 layers. But will the total time in factory still not be less for one 32 layer chip than two 16 layer chips?

I imagine there must be certain manufacturing steps that are "fixed overhead" regardless of the number of layers.

Interesting point, so will a 32 layers based SSD have twice the capacity of a 16 layers but cost less than two of them? If it works the better for us.
The only problem I see with 3d stacking is that heat density cannot go but up. Reducing clockspeed and all works until a certain point, then it's again smaller nodes only that reduce power consumption at the same layers amount.

 

[Enigmoid]

One interesting detail that I noticed is Intel's projection of 10nm (= foundry's 2nd gen FF) HVM.

They project it at mid-2017. Also note the absence of projections for their own 10nm. They seem to know better what the competition will do than themselves! They don't want influence TSMC and Samsung, do they?

And for those who have not seen it, another great slide from Intel about consolidation (page 60): http://intelstudios.edgesuite.net/im/2014/pdf/2014_Intel_IM_Smith.pdf

I can't read I but aren't those projections from the research papers quoted on the side there?

 

[witeken]

I can't read I but aren't those projections from the research papers quoted on the side there?

Yes they are. You can find a higher res version in the PDF of the presentation.

--

Intel's Kirk Skaugen says their IGPs are already faster than 80% of the dGPUs in the market. There were some rumors of a Broadwell-K delay, but he refers to the (GT3) product that will offer a 100X increase since 2006 to be available early 2015.