Yea, I agree. I am far from an expert on this, but IMO, intel needed 14nm to be a compelling product in mobile, cheap and efficient enough to overcome their lack of integration. Instead they got delay after delay, poor yields, and mediocre performance. Their is a lot of criticism of Sklylake for lack of performance gains, but to me, nothing is more disappointing than 14nm atom.
Do you know what designing a CPU architecture to run at twice the frequency does to density?
Maybe for a chip that was designed using min VCC, max length transistors, and ultra high vt cells you could double your frequency by adjusting those variables, however - You're assuming Apple is using all high-vt cells for their A9, I highly doubt that is the case.
"Just" changing VTs and voltages doesn't mean your density won't take a hit. As you say you can use overdrive voltages, but chip size is still going to increase when you have to widen your clock nets and power grid for reliability at higher voltages and when your route dominated paths don't scale anywhere close to 2x from voltage and you have to start widening or adding drive cells.
Nobody bins for FF in mobile either, at least that I'm aware of. Maybe Apple has cash to burn on low yields though
They do. The high performance CPU 14nm process is known as P1272, and the SoC process (which offers transistor/interconnect options that span low power to high performance and very dense to not-so-dense) is known as P1273.
do we know if skylake core m uses p1273(low power, high density) or p1272 (high performance) process ?
p1272.
I think Intel would be well served with a Skylake Core M based on P1273 process. I am thinking Intel is forced to use P1272 because of the very high turbo boost clocks on the top of the line Core M m7 SKUs. We know that Intel is using the high performance process to reach those higher clocks. But in the sub 5W space Intel is better off optimizing for highest power efficiency than high turbo clocks in excess of 3 Ghz. I think with a P2173 design then Intel will be able to go after sustained peak performance without throttling rather than bursty performance.
Apple has shown with A9/A9X that a wide CPU with 1.85- 2.26 Ghz clocks built on a high density low power process is great for performance and efficiency. A9's key advantage is sustained performance without throttling even after hours of benchmarking. Intel can also go for larger caches with a high density process which would increase IPC as most apps benefit from high speed low latency caches.
So what you're saying is that they should make an Atom architecture that doesn't suck and is targeted specifically at these low power levels. I agree.
Actually I am saying Intel should ditch Atom and use their big cores to power their entire product line from smartphones/tablets to desktops/notebooks and servers/workstations. The low power high density design should be used in phones and tablets and the high performance design should be used in the rest of the product stack. There can be CPU core level differences (like AVX 512 and other server features) for CPU cores used in server and workstation chips. But the core microarchitecture can be same across the entire product stack. It would be awesome.
Or alternatively, it would make the Snapdragon 810 look like the paragon of efficiency. We don't know enough about how well the core scales to know if it is any good for phones. I'm sure Intel has run the simulations.
Actually I am saying Intel should ditch Atom and use their big cores to power their entire product line from smartphones/tablets to desktops/notebooks and servers/workstations. The low power high density design should be used in phones and tablets and the high performance design should be used in the rest of the product stack. There can be CPU core level differences (like AVX 512 and other server features) for CPU cores used in server and workstation chips. But the core microarchitecture can be same across the entire product stack. It would be awesome.
However the Atom line now is so bad that is time to put the Core line on the front lines and move the Atoms on the only place they can deal some good performance: Xeon PhiThe Atom line used to be much more IP friendly than the Core line, this alone would be a deal breaker on the mobile market.
Yeah, or some high density variant, like they have seperate Skylakes for Core i and Xeon.However the Atom line now is so bad that is time to put the Core line on the front lines and move the Atoms on the only place they can deal some good performance: Xeon Phi
From a business and brand perspective the density bs from Intel seems very strange. Ofcource they know its wrong but why use this pr crap nobody with insight beliefs?
At Intel's Investor meeting they tell the public that the A9 (from TSMC)
has a lower (??!!) transistor density as the A8.
One wonders if they really belief that themselves?
The L3 goes from 4MB to 8MB
The L2 goes from 1MB to 3MB
Only the extra cache brings in 360+ million transistors
increasing the transistor count by almost 20%.
Then there is the increase in GPU increase from four
series 6 clusters to six series 7 clusters. A series 7
is significantly more powerful per cluster clock for clock
as a series 6 cluster. Then add in all the new extra series
7 features like for instance hardware tesselation.
The real transistor density should be 15% or more higher
at least considering of all the added SRAM. The image
below corrects the bar graph further using Intel's own
BDW2+2 numbers (1.3 Billion transistors on 82mm2)
Still being conservative here, A9 densities may be higher.
Only the extra cache brings in 360+ million transistors
increasing the transistor count by almost 20%.
Are you saying each cache bit uses 45 transistors in average?
At Intel's Investor meeting they tell the public that the A9 (from TSMC)
has a lower (??!!) transistor density as the A8.
One wonders if they really belief that themselves?
The L3 goes from 4MB to 8MB
The L2 goes from 1MB to 3MB
Only the extra cache brings in 360+ million transistors
increasing the transistor count by almost 20%.
Then there is the increase in GPU size from four
series 6 clusters to six series 7 clusters. A series 7
cluster is significantly more powerful clock for clock
as a series 6 cluster. Then add in all the new extra series
7 features like for instance hardware tesselation.
The real transistor density should be 15% or more higher
at least considering all the added SRAM. The image
below corrects the bar graph further using Intel's own
BDW2+2 numbers (1.3 Billion transistors on 82mm2)
Still being conservative here, A9 densities may be higher.
The A9 has 4 megabytes more L3 Cache and 2 megabytes
more L2 cache compared to the A8.
6 megabytes in total makes 48 megabits Then add extra
buffers, cache tags and so on.
It's not misleading if they are using minimum channel length in comparisons. Rather than using production nominal channel length in the comparisons.You should contact the SEC if you believe Intel is intentionally misleading/lying to its investors.