Exactly. Intel realizes the threat that TSMC and the ARM ecosystem along with AMD/GF poses to its cash cow DCG. Intel's 10nm and TSMC 7nm / GF 7nm are for all intents and purposes going to be competing in the same time frame when it comes to server products. Intel realizes that it cannot drag its feet going forward as there are hungry competitors who will move to the bleeding edge nodes at the earliest possible time. Intel is just acknowledging that their past methods will not work going forward.
Exactly. Intel realizes the threat that TSMC and the ARM ecosystem along with AMD/GF poses to its cash cow DCG. Intel's 10nm and TSMC 7nm / GF 7nm are for all intents and purposes going to be competing in the same time frame when it comes to server products. Intel realizes that it cannot drag its feet going forward as there are hungry competitors who will move to the bleeding edge nodes at the earliest possible time. Intel is just acknowledging that their past methods will not work going forward.
The issue was known before that drop, both factual and indirectly from the ER. So I thought someone said something negative/less expected during the meeting.Its related to the Atom issues for the C2000.
7nm DCG in 2020 would be unreal!What are you saying? In the last thread where we had a discussion, I told you to expect Intel to move DCG/HEDT to leadership on nodes, and you vehemently disagreed with me telling name that they need to do small dies first.
Intel said at the conference that DCG product node leadership will begin with 10nm++, not 7nm.
This fits the roadmap that mikk showed us on this forum. Ice Lake-EP will possibly be out on 10nm++ in 2019 and Sapphire Rapid on 7nm in 2020.
Arachnotronic gave the correct reason: Intel lowered DCG operating margins forecasts.The issue was known before that drop, both factual and indirectly from the ER. So I thought someone said something negative/less expected during the meeting.
Considering what Kaby Lake brought to the table, and considering 8th Gen is a tick , I imagine it's 15% better performance under a limited power envelope. Kaby Lake did the same for CPU's under 35W/15W. 8700K is probably not much better than Kaby Lake was from Skylake.During its annual investors day, Intel shed some light on upcoming Cannonlake architecture. The company promises over 15 percent better performance compared to Kabylake. While no exact numbers were shared, it was told that they are based on SysMark benchmark.
More importantly, Intel Cannonlake is currently expected to ship in the second half of 2017. This probably means entry-level parts with faster CPUs coming at a later date.
It’s also worth noting that the slide below is clearly comparing i7 series, a direct competitor to AMD Ryzen, which is expected to launch later this month.
So another group is going to look much better with wafer costs and R&D reduced there...DCG margins? CPU = very high margins, so as adjacencies become bigger, margins go down. Also, because DCG goes to leading edge first, it has higher wafer cost and takes a bigger burden of R&D on its name.
Intel has never denied competition. Secondly, it makes a thousand times more sense for a company to put its growing businesses on the leading edge than a stagnant, albeit big, one.Arachnotronic Intel's change of tactics is a forced one and basically acknowledges that there is serious competition coming at them from both AMD and the likes of Qualcomm and other ARM designers.
Arachnotronic Intel's change of tactics is a forced one and basically acknowledges that there is serious competition coming at them from both AMD and the likes of Qualcomm and other ARM designers. All these companies will move to bleeding edge nodes at the earliest possible timeframe. The big problem for Intel is their process leadership is basically gone. Apple is bankrolling TSMC's rapid march to 7nm and 5nm. GF with the help of IBM is capable of staying close behind Intel / TSMC. We will see Intel 10nm server chips and TSMC 7nm based Qualcomm server chips along with GF 7nm based AMD server chips in 2019. If Intel were to stick with their old model of 18 month lag in moving server CPUs to the latest nodes that could pose serious problems as their competitors keep moving to the latest TSMC and GF nodes as they are available.
The question I think Intel needs to answer is how are they going to yield massive dies at 7nm if they are going first to server. I think the first generation chips are going to be shrinks with no major core count increases. So if Intel have a 10nm++ chip at 500 - 600 sq mm then at 7nm it should be around 300 sq mm. That would allow them to yield well and use the learning to ramp up die sizes in the second and third iterations.
Yeah, as Swan said it's a zero sum game. In the past the losses went to mobile ("Intel wasted $10B in mobile", which is a big exaggeration), now they're going to DCG.So another group is going to look much better with wafer costs and R&D reduced there...
Explain the benefits of EMIB vs MCM?They aren't going to need to yield massive dies. They are going to "chop up" the dies and stitch them back together using EMIB packaging. Intel says that it will be virtually indistinguishable from a monolithic die, none of the issues associated with traditional MCM.
Amazing technology, maybe you now have your answer about what Intel has been doing for all these years.
The EMIB tech is key to Intel's new "data center first" strategy.
Explain the benefits of EMIB vs MCM?
First I'm hearing of EMIB, sounds interesting.
EMIB aka 2.5D is Intel's solution for 3D integration. The interposer tech that for instance AMD has used for HBM is expensive. Intel's solution is as cheap as possible, but has same advantages. You use it to basically create a giant die by 3D stacking / connecting.Explain the benefits of EMIB vs MCM?
First I'm hearing of EMIB, sounds interesting.
http://www.intel.com/content/www/us/en/foundry/emib.html
Check this out, it's like interposers on steroids and without the limitations
Looks pretty damn great for creating very large CPU's. If for example AMD were to create a 6-8 die Naples CPU, they would probably have to use technology like this.http://www.intel.com/content/www/us/en/foundry/emib.html
Check this out, it's like interposers on steroids and without the limitations
What TSVs? You mean what you're seeing on the packaging substrate which isn't silicon?I find it amusing that they show 4x layers of TSVs on Intels EMIB but they say they dont have any additional cost from TSVs
What TSVs? You mean what you're seeing on the packaging substrate which isn't silicon?