Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Hitman928]

That curve is bs, it s just PL2 that is increased to boost the score.

In the new curve we can see that from 20W to 40W the score increase from 9500 to roughly 14500, that s 61% higher perf for 2x the power and that s just impossible by the very laws of semiconductors physics.

61% higher perf require 3x the power with a very good process that scale close to a square law wich is the theorical best case for mosfets, so this curve is just made up, anyone with some knowledge of electronics will spot such a discrepancy.

I believe this talk of a, "scheduler" issue is a red herring due to a poor translation. I don't think it has anything to do with the scheduler at all but rather how much the power load is balanced between the P and E cores which has its largest effect in lower power situations. In other words, when power limited, adjusting the point of operation along the f/v curve for the P and E cores to maximize performance. This isn't as straight forward as a typical perf/power curve with only 1 type of core.

 

[Abwx]

There was a scheduling issue in the old pcode, you are wrong. You can see this also in the updated ultrabookreview Cinebench scores where it scored 12.1K after 10 Minutes at 28W.

Dosnt matter, 60% higher perf for 2x the power doesnt happen unless the starting point is very low power when uncore power is significant.

Beside ultrabookreview make no power measurements but we can see in his HVInfo screens that the CPU is set to 30W with boost at 64W or 50W depending of the screen, if the cooling apparatus is efficient then the CPU can boost to more than 30W even after 10mn.

No, it's quite possible and doesn't violate any laws of semiconductor physics.

The 7840HS result in that graph goes from ~8k at 15W to ~13k at 30W. That's also roughly 61% increase in performance for 2x the power. And those data points match up with other reviews.

If the uncore use 5W then from 15 to 30W that s 10 to 25W devoted to the cores, so 2.x higher power for the cores, in the case of MTL that s 2.25x, although both figures seems grossly measured.

With respect to semiconductor physics, keep in mind that power is linear with frequency and squared with voltage. So it's expected to have closer to linear scaling at lower power levels where the percentage increase in voltage is smaller for a given percentage increase in frequency.

It s the other way around, to extract 2x the frequency you have to increase voltage by sqrt(2) assuming that s perfect mosfets, in real life that s a little than sqrt(2).

Increasing voltage by sqrt(2) increase power by 2x even if frequency is left unchanged, if this latter is raised by 2x as allowed by the voltage increased by sqrt(2) then the total will be 4x the power at 2x the frequency, of course that s an ideal case that do not exist in real semiconductors, it s somewhat more than 4x the power.

 

[H433x0n]

Dosnt matter, 60% higher perf for 2x the power doesnt happen unless the starting point is very low power when uncore power is significant.

Beside ultrabookreview make no power measurements but we can see in his HVInfo screens that the CPU is set to 30W with boost at 64W or 50W depending of the screen, if the cooling apparatus is efficient then the CPU can boost to more than 30W even after 10mn.


If the uncore use 5W then from 15 to 30W that s 10 to 25W devoted to the cores, so 2.x higher power for the cores, in the case of MTL that s 2.25x, although both figures seems grossly measured.



It s the other way around, to extract 2x the frequency you have to increase voltage by sqrt(2) assuming that s perfect mosfets, in real life that s a little than sqrt(2).

Increasing voltage by sqrt(2) increase power by 2x even if frequency is left unchanged, if this latter is raised by 2x as allowed by the voltage increased by sqrt(2) then the total will be 4x the power at 2x the frequency, of course that s an ideal case that do not exist in real semiconductors, it s somewhat more than 4x the power.

You’re ignoring that the same type of curve behavior existed on RPL-H and MTL pre pcode update.

 

[Abwx]

You’re ignoring that the same type of curve behavior existed on RPL-H and MTL pre pcode update.

But Intel 7 is not the same as Intel 4, its curve is less concave because the process is better in matter of relative frequency/voltage scaling, remember that it was refined at least twice.

Of course RPL s less efficient but the shape of the curve is much better, indeed Intel 4 has lower max frequency, wich mean that it should bend earlier than RPL when power is increased.

Edit : If we dig in the curve we can see that from 17W to 50W frequency is increased 2x given that the score is 2x, but power increase only by 3x while 4x would be already a miracle, this curve is ridiculous, but for sure that it can fool a lot of unsuspecting readers, all he did was to copy RPL curve and translate it higher in the graph.

 

[cebri1]

If it's an increase in PL2 power it should be easily measurable. But if it's only that, there no need to release the initial bios without it.

 

[SiliconFly]

...So the only time the LPE tile advantage can come into play is when not interacting with the laptop at all. Even just browsing the web, typing in Word, or checking email will keep the compute tile powered up...

Thats incorrect. System idle is not only when a user is not interacting. It happens a lot when using apps.

Current OSes (like Windows) are built in such a way that when active application threads go idle, the entire system goes to idle state. When using apps like Word or Excel or Browser, or Composing an email, the CPU tile can be turned off most of the time when the user isn't interacting, like typing or scrolling or clicking, which is most of the time, like more than 95% of the time actually.

When we click on a keyboard key, the main thread is woken up and executes for less than a millisecond. The system idles for the rest of the 99.9% of the time (while typing in word/excel/email/browser).

While browsing we scroll or click links. Scrolling video refresh is handled by the SoC tile leaving the CPU tile idle. CPU tile is off most of the time while scrolling. No need to wake up.

Clicking links is a bit more CPU intensive than a simple key press. While a new page loads or a simple (Ctrl-R) refresh happens, the CPU needs to parse all the web elements linked to the page which is a bit CPU intensive. The CPU tile will be up for a few seconds at best until the main elements finish loading and the rest of the lesser processing can be easily handled by the LP E cores after that. But people don't tend to click on links more than a few times per minute. Not an issue.

So, even while an average user is using word or excel or browser or email, the system will still idle more than 95% of the time. It's the way current breed of operating systems are designed. Fully event driven. And mostly idling.

 

[Hitman928]

Thats incorrect. System idle is not only when a user is not interacting. It happens a lot when using apps.

Current OSes (like Windows) are built in such a way that when active application threads go idle, the entire system goes to idle state. When using apps like Word or Excel or Browser, or Composing an email, the CPU tile can be turned off most of the time when the user isn't interacting, like typing or scrolling or clicking, which is most of the time, like more than 95% of the time actually.

When we click on a keyboard key, the main thread is woken up and executes for less than a millisecond. The system idles for the rest of the 99.9% of the time (while typing in word/excel/email/browser).

While browsing we scroll or click links. Scrolling video refresh is handled by the SoC tile leaving the CPU tile idle. CPU tile is off most of the time while scrolling. No need to wake up.

Clicking links is a bit more CPU intensive than a simple key press. While a new page loads or a simple (Ctrl-R) refresh happens, the CPU needs to parse all the web elements linked to the page which is a bit CPU intensive. The CPU tile will be up for a few seconds at best until the main elements finish loading and the rest of the lesser processing can be easily handled by the LP E cores after that. But people don't tend to click on links more than a few times per minute. Not an issue.

So, even while an average user is using word or excel or browser or email, the system will still idle more than 95% of the time. It's the way current breed of operating systems are designed. Fully event driven. And mostly idling.

That is not the understanding given by the Geekerwan guy but I look forward to the test results that prove you correct.

 

[Abwx]

When we click on a keyboard key, the main thread is woken up and executes for less than a millisecond. The system idles for the rest of the 99.9% of the time (while typing in word/excel/email/browser).

No CPU can boost frequency in a matter of 1ms, let alone wake up cores and then boost frequency, even if at an average value, in such a short time.

How Quickly do CPUs Change Clock Speeds?

We often see very high clock frequencies listed for our CPUs. But CPUs don’t run at maximum clock all the time in order to reduce power consumption and heat generation. They also can’t instantly go…

chipsandcheese.com

 

[SiliconFly]

That is not the understanding given by the Geekerwan guy but I look forward to the test results that prove you correct.

Then it looks like the Geekerwan person lacks understanding of how OSes, threads, schedulers, thread director, etc works. After all, looks like he's already claimed LP E cores required special programming, which is completely wrong. Understanding of system internals like os design, threads, opcode, cpu interrupts, etc are a prerequisite.

 

[H433x0n]

But Intel 7 is not the same as Intel 4, its curve is less concave because the process is better in matter of relative frequency/voltage scaling, remember that it was refined at least twice.

Of course MTL s less efficient but the shape of the curve is much better, indeed Intel 4 has lower max frequency, wich mean that it should bend earlier than RPL when power is increased.

Edit : If we dig in the curve we can see that from 17W to 50W frequency is increased 2x given that the score is 2x, but power increase only by 3x while 4x would be already a miracle, this curve is ridiculous, but for sure that it can fool a lot of unsuspecting readers, all he did was to copy RPL curve and translate it higher in the graph.

So what happens 4-6 weeks from now if these results are reproduced by multiple people with the updated pcode? Will they all be lying?

 

[SiliconFly]

No CPU can boost frequency in a matter of 1ms, let alone wake up cores and then boost frequency, even if at an average value, in such a short time.

How Quickly do CPUs Change Clock Speeds?

We often see very high clock frequencies listed for our CPUs. But CPUs don’t run at maximum clock all the time in order to reduce power consumption and heat generation. They also can’t instantly go…

chipsandcheese.com

To wake up an idle CPU tile and boost it to max frequency is something new to MTL. I have no idea how much time it takes for the full frequency ramp up to happen. But I know for sure, the CPU tile can be turned off very easily when the system starts to idle as it's one of the primary purposes of the thread director. A hardware context switch takes around a millisecond to migrate a thread context from the CPU tile to a LP E core.

LP E cores is the key strength of MTL. It's all about idling and efficiency (even while using many of the aforementioned apps).

 

[Abwx]

So what happens 4-6 weeks from now if these results are reproduced by multiple people with the updated pcode? Will they all be lying?

I once told you a few time ago and before it was launched that MTL wouldnt cut the mustard, wich you negated...

So far the only thing that will happen is enhanced power profiles such that the chip will score higher but with more power boost, some make up to make things look better but since it s the same silicon there s nothing more to expect untill some Intel 4+ or even 4++ since it look to be eventually cmparable to TSMC s N6 but certainly not as efficient as TSMC s N5, let alone N4.

A hardware context switch takes around a millisecond to migrate a thread context from the CPU tile to a LP E core.

What you are talking about is possible only if all concerned cores are awaken, in this case you can switch threads in a very short time, here we re talking to send a thread to a sleeping core, you must fire it and then increase its base frequency, this take way more time than 1ms.

 

[Hitman928]

Then it looks like the Geekerwan person lacks understanding of how OSes, threads, schedulers, thread director, etc works. After all, looks like he's already claimed LP E cores required special programming, which is completely wrong. Understanding of system internals like os design, threads, opcode, cpu interrupts, etc are a prerequisite.

He didn't say that LPE cores require special programming, he said that was an option for utilizing them. Waking up a whole tile with the requirement to bring up all the voltages and clocks will take a significant amount of response time. I really don't think Intel is trying to power off the CPU tile whenever there's a short amount of idle time, but again, if there is any testing proving this I am open to seeing it. So far, everything we have points to it either not being the case or being completely broken though.

 

[SiliconFly]

He didn't say that LPE cores require special programming...

Your own quote (possibly a snippet from Geekerwan):
The two ultra-low power small cores. . . will not be used in daily applications. They can only be used in standby idle state, when watching videos locally [not streaming], or in the software specially programmed for them

...I really don't think Intel is trying to power off the CPU tile whenever there's a short amount of idle time...

Thats the whole idea

...So far, everything we have points to it either not being the case or being completely broken though...

True. We haven't seen enough tests that primarily stress the LP E cores without stressing out the CPU tile too much (which'll be more in line with real world usage). I'm waiting too.

 

[mikk]

So far the only thing that will happen is enhanced power profiles such that the chip will score higher but with more power boost

You are spreading FUD unless you finally can prove your claim which you can't. Once again, after updating the bios Ultrabookreview got 1000 points more at 28W - there is no PL2 involved after 10 minutes. This score also is roughly in-line with the 28W score from Golden pig.

 

[igor_kavinski]

I think the lack of user configurability hurts MTL's usefulness. It would've been nice to be able to specify to use only E-cores and LP cores when on battery to maximize battery time. Skylake level performance is NOT bad for most tasks. Heck, I'm on an Ivy Bridge laptop as my daily driver. Intel dumbs its technology down for the average user which is just the wrong way of going about it. If you give people options, they will learn to take advantage of them, especially if the benefits are prominently tangible.

 

[Hulk]

Thats incorrect. System idle is not only when a user is not interacting. It happens a lot when using apps.

Current OSes (like Windows) are built in such a way that when active application threads go idle, the entire system goes to idle state. When using apps like Word or Excel or Browser, or Composing an email, the CPU tile can be turned off most of the time when the user isn't interacting, like typing or scrolling or clicking, which is most of the time, like more than 95% of the time actually.

When we click on a keyboard key, the main thread is woken up and executes for less than a millisecond. The system idles for the rest of the 99.9% of the time (while typing in word/excel/email/browser).

While browsing we scroll or click links. Scrolling video refresh is handled by the SoC tile leaving the CPU tile idle. CPU tile is off most of the time while scrolling. No need to wake up.

Clicking links is a bit more CPU intensive than a simple key press. While a new page loads or a simple (Ctrl-R) refresh happens, the CPU needs to parse all the web elements linked to the page which is a bit CPU intensive. The CPU tile will be up for a few seconds at best until the main elements finish loading and the rest of the lesser processing can be easily handled by the LP E cores after that. But people don't tend to click on links more than a few times per minute. Not an issue.

So, even while an average user is using word or excel or browser or email, the system will still idle more than 95% of the time. It's the way current breed of operating systems are designed. Fully event driven. And mostly idling.

I'm not sure if this proves or disproves anything but while I'm sitting here simply reading this post and typing a reply, during that time interval the average clock as reported by HWinfo is 3200MHz while the average effective clock is 350MHz. Since the average effective clock is defined to be the clock cycles where the processor is actually executing instructions. This data would seem to indicate that the CPU is doing very little while reading/replying to a forum thread.

 

[SiliconFly]

So far the only thing that will happen is enhanced power profiles such that the chip will score higher but with more power boost, some make up to make things look better but since it s the same silicon there s nothing more to expect untill some Intel 4+ or even 4++ since it look to be eventually cmparable to TSMC s N6 but certainly not as efficient as TSMC s N5, let alone N4.

Anandtech and toms hardware themselves put Intel 4 ahead of TSMC N5. And Semiwiki & wikichip too. Absolutely no confusion there.

What you are talking about is possible only if all concerned cores are awaken, in this case you can switch threads in a very short time, here we re talking to send a thread to a sleeping core, you must fire it and then increase its base frequency, this take way more time than 1ms.

1 ms is a very long time in terms of CPU. The frequency ramp up/down happen in microseconds not ms or seconds. A full ramp up from zero might take up to 1 ms worst case.

 

[Hulk]

I think the lack of user configurability hurts MTL's usefulness. It would've been nice to be able to specify to use only E-cores and LP cores when on battery to maximize battery time. Skylake level performance is NOT bad for most tasks. Heck, I'm on an Ivy Bridge laptop as my daily driver. Intel dumbs its technology down for the average user which is just the wrong way of going about it. If you give people options, they will learn to take advantage of them, especially if the benefits are prominently tangible.

Or perhaps in Windows Setting a slider to control how aggressively Windows will stay on the LPE cores? It could go from one extreme being, "Stay on the LPE's no matter what" all the way to "Move to the CPU tile when the LPE cores are 50% loaded." Or something like that. This way if you are on a flight or something you can simply force the system to remain in a really low power mode, which isn't a big deal if you're watching a movie or doing Office work.

Anandtech boards once again saving the world

 

[SiliconFly]

I'm not sure if this proves or disproves anything but while I'm sitting here simply reading this post and typing a reply, during that time interval the average clock as reported by HWinfo is 3200MHz while the average effective clock is 350MHz. Since the average effective clock is defined to be the clock cycles where the processor is actually executing instructions. This data would seem to indicate that the CPU is doing very little while reading/replying to a forum thread.

Very very true.

Most people don't take time to examine, but we can all do it ourselves in Windows very easily in task manager itself. CPU usage will be at 1% most of the time (just pin it to top in its settings and resize).

The crazy part is, it's actually a lot less than 1%, but Windows task manager rounds it up to a whole number.

This kinda extreme light load (apps idling) can be very comfortably handled by LP E cores completely. Actually, the two LP E cores should be able to handle a lot more load than just the simple idling apps.

 

[Khato]

It s the other way around, to extract 2x the frequency you have to increase voltage by sqrt(2) assuming that s perfect mosfets, in real life that s a little than sqrt(2).

Sorry, but this statement is fundamentally flawed. It may be a gross approximation provided in entry level EE courses, but that doesn't make it correct. Feel free to look at the V/F curve of any modern processor to disprove. eg the 12700k in this video -

- goes from .775V at 2GHz to 1V at 4Ghz, so about sqrt(1.66) voltage increase for 2X frequency. Meanwhile it goes from .825V at 2.5GHz to 1.35V at 5Ghz, which is about sqrt(2.67) voltage increase for 2X frequency.

I'm not going to attempt to explain in further detail than that though. While I recall the basics from an advanced semiconductor fundamentals course, since I don't work directly on process development or structural design I've long since forgotten the nuances necessary to provide a proper explanation.

 

[Philste]

source?

You literally posted it yourself one month ago

I haven't seen any LNL die shots, where did you see the layout?

Uh, I think people don't like linking twitter stuff here, so here:

Look where the L3/LLC is

Also I knew it even before that:

 

[SiliconFly]

Or perhaps in Windows Setting a slider to control how aggressively Windows will stay on the LPE cores? It could go from one extreme being, "Stay on the LPE's no matter what" all the way to "Move to the CPU tile when the LPE cores are 50% loaded." Or something like that. This way if you are on a flight or something you can simply force the system to remain in a really low power mode, which isn't a big deal if you're watching a movie or doing Office work.

Anandtech boards once again saving the world

Thats transparently handled by the thread director. I don't think there's a way for users to configure how the cores are scheduled by the thread director as of now. But it'll definitely be a welcome addition. Someone should reach out to Intel.

 

[Hitman928]

Your own quote (possibly a snippet from Geekerwan):
The two ultra-low power small cores. . . will not be used in daily applications. They can only be used in standby idle state, when watching videos locally [not streaming], or in the software specially programmed for them

Not sure why you think that quote is incongruent with what I am saying. The quote is stating where the LPE will be used with the current scheduler/firmware/thread director, then gives another option that if the LPE cores are to be used outside of those circumstances, the apps will need to be programmed specifically to use them. What do you see as incorrect?

 

[H433x0n]

I once told you a few time ago and before it was launched that MTL wouldnt cut the mustard, wich you negated...

So far the only thing that will happen is enhanced power profiles such that the chip will score higher but with more power boost, some make up to make things look better but since it s the same silicon there s nothing more to expect untill some Intel 4+ or even 4++ since it look to be eventually cmparable to TSMC s N6 but certainly not as efficient as TSMC s N5, let alone N4.

So you believe GoldenPig doesn’t know how to limit power and chart a curve in 5W increments?
You also believe UltraBookReview is incapable of accurately measuring performance at a fixed power draw.

What happens if NoteBookCheck gets the same results with updated pcode? Will they also be incapable of measure a perf/watt curve?