Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Exist50]

@Exist50 The extra clocks covering 33% lack of cores are next to impossible unless you are expecting Meteorlake to clock 6GHz+, and all core Turbo at that! They aren't using magic to get those clocks, it's still mostly getting it from using bricks as heatsinks and water cooling being common.

It's not a 33% gap though. If we use a rough estimate of 4 E-cores = 2 P-cores in MT, than that's 14 P-core equivalent for MTL-S and 16 RPL-S. So it would only have to be ~14% more performance @ iso-power, well within typical ranges for a full node shrink.

Some are calling for firing of Riviera(head of DC) that came in just few months ago, etc, etc.

Riviera is head of the server business group, not the engineering group. IIRC, that's Gloria Leong.

A 6-P-core meteor lake that has an improved memory system and improved process for the CPU die

Therein lies the problem.

 

[Exist50]

If Intel wants to counter Bergamo with E cores there is a lot to catch up to though. I'd think Intel should better have spent the time to make P cores more area efficient. As is E cores are barely competitive in INT workloads, and worlds behind in FP ones.

An E-core based chip should be extremely competitive vs Bergamo. Not sure what you're talking about here. Also, cloud is more int heavy than FP.

I'm actually curious about this. As soon as I'm done with my college apps I might just do a bunch of napkin math to see how bad it really is haha, unless you know someone who already has done something similar to this?

Good luck on your apps!

 

[Exist50]

SemiAnalysis shows a 25.17% Area reduction as a whole when compared to Golden Cove. If Redwood Cove brings 25% IPC there will be no gains in Performance/Area

Bruh, you got your math a bit mixed up there...

Any area reductions vs Golden Cove, at the same IPC, will improve perf/area. Then any extra IPC they can fit within that same new area will provide additional perf/area. You divided where you should have multiplied.

But regardless, I don't think there's much point in talking about area efficiency gains between nodes. RWC vs Zen 4 and Zen 5 will be the matchup, and those should be roughly similar processes.

 

[IntelUser2000]

Riviera is head of the server business group, not the engineering group. IIRC, that's Gloria Leong.

Yea posters at Inquirer were calling for that. You can't make any noticeable(to the public) changes in that time. It's not possible.

 

[moinmoin]

Some members here predicted that Crestmont will have a configurble cache system.

Well is that what this is?

https://twitter.com/x/status/1589808451068518403

"Configurable" as in more room for even more segmentation I guess?

An E-core based chip should be extremely competitive vs Bergamo. Not sure what you're talking about here. Also, cloud is more int heavy than FP.

Even if we pretend that only INT matters I expect the lower ST peak performance will make E cores less competitive and more comparable to massive multi-core ARM chips and systems. But we will see, first Bergamo has to launch and then we will see how much urgency Intel feels to launch an "extremely competitive" E cores based chip in Sierra Forest.

 

[BorisTheBlade82]

"Configurable" as in more room for even more segmentation I guess?


Even if we pretend that only INT matters I expect the lower ST peak performance will make E cores less competitive and more comparable to massive multi-core ARM chips and systems. But we will see, first Bergamo has to launch and then we will see how much urgency Intel feels to launch an "extremely competitive" E cores based chip in Sierra Forest.

On a core per core base Bergamont will surely have more performance than Sierra Forest. But that will not be the top priority. The bigger question is, how many cores Intel will pack and how PPA will turn out. Also SMT might not be important as it is often turned off in cloud/virtualization environments.

 

[LightningZ71]

Therein lies the problem.

Given Intel's recent track record for releases, I don't see that being a problem. 10th to 11th was an improved IMC and a tweak to 14nm for higher clocks. 11th to 12th was a move from 14nm to Intel7, DDR5 support and an improved cache system. 11th to 12th was a move to a further refined Intel7, more cache, and high speed DDR5 DRAM support. I see no problem with Meteor Lake having a further improved process and better memory controller performance.

 

[nicalandia]

I'm not following? I'm missing something because based on the data you presented it seems like even if Golden/Raptor have the same IPC as Redwood then there is a 25% reduction in area for equal performance. Performance/Area gains will be even larger if Redwood has a better IPC than Golden/Raptor.

Bruh, you got your math a bit mixed up there...

Sorry, I ment no gains against AMD Zen cores(a few post earlier someone was pointing out about Intel needing to have better performance/area than AMD)

Zen3 is 4 mm^2 vs Golden Cove 7 mm^2
Zen4 is 3.84 mm^2 vs Raptor Cove 8 mm^2
Zen5 will be about 3.4 mm^2 vs Redwood Cove 5.33 mm^2

Looks like Crestmont is going be actually different than Gracemont.

Their design appear to be Identical in principle(shared L2, clusters and internal Ring)

 

[Hulk]

Zen3 is 4 mm^2 vs Golden Cove 7 mm^2
Zen4 is 3.84 mm^2 vs Raptor Cove 8 mm^2
Zen5 will be about 3.4 mm^2 vs Redwood Cove 6 mm^2

Every time I see these numbers I'm stunned. Gotta give credit where it's due. AMD and TSMC pulled off a freakin' magic act with Zen 4. Tiny, powerful, and efficient.

 

[nicalandia]

Every time I see these numbers I'm stunned. Gotta give credit where it's due. AMD and TSMC pulled off a freakin' magic act with Zen 4. Tiny, powerful, and efficient.

And... they are about to pull another rabbit out of that Hat, called Zen4c which I predict to be somewhere about 30% smaller than Zen4

 

[moinmoin]

On a core per core base Bergamont will surely have more performance than Sierra Forest. But that will not be the top priority. The bigger question is, how many cores Intel will pack and how PPA will turn out. Also SMT might not be important as it is often turned off in cloud/virtualization environments.

If PPA were the sole priority ARM would dominate servers since years. Instead in the last couple of years it turned out that even on servers many workloads are limited by ST performance, and it's there that there has been some surprising demand for higher frequency server parts. As such if Sierra Forest is significantly below the ST peak performance of Xeon P core chips I don't expect it to see much use. Bergamo on the other hand I expect to strike a balance that's more interesting to much of the server audience: higher efficiency and higher PPA, but same feature set and in all-cores loads likely peak frequencies pretty close to full fat server Zen 4 cores. I agree SMT is not of any significant importance here though.

 

[BorisTheBlade82]

@moinmoin
Lest not forget that the transition of use cases from x86 to ARM is more than just switching some hardware - so IMHO this is not the best comparison. In general I certainly agree with you that Sierra Forest needs a certain amount of Oomph in order to be worthwhile.
But if (big if) Intel could price a 256c Sierra Forest comparably to a 128c Bergamo, this would be a clear winner (assuming not too shabby efficiency).

 

[DrMrLordX]

I'm not following? I'm missing something because based on the data you presented it seems like even if Golden/Raptor have the same IPC as Redwood then there is a 25% reduction in area for equal performance. Performance/Area gains will be even larger if Redwood has a better IPC than Golden/Raptor.

Was gonna say the same thing. Wut?

Sorry, I ment no gains against AMD Zen cores(a few post earlier someone was pointing out about Intel needing to have better performance/area than AMD)

The goal for the Core team would be to improve the area efficiency of Core vs. the -mont Atom cores so that Intel at least can start looking at consumer chips with more P cores in the future. It's going to be hard for them to catch AMD since, at least for now, AMD has efficient designs and, shall we say, interestingly flexible nodes.

Dang, we haven't seen that much L2 cache since Core 2.

If I recall, Conroe et. al had l2 shared between cores, which is one of the reasons why it got so big (and why it was so darn useful).

 

[nicalandia]

But if (big if) Intel could price a 256c Sierra Forest comparably to a 128c Bergamo, this would be a clear winner (assuming not too shabby efficiency).

Will Sierra Forest Scale to more than 1P? Will there be 2S, 4S? I don't believe that has been shared yet.

 

[Hulk]

This is how Intel has programmed P and E core frequencies in my 13900K for various power limits.
Unfortunately I'm starting to throttle at 225W so that is as far as I can go with this.
Strange little reversal of E/P frequencies at 40W. I'm going to investigate that area further.
Raptor Lake is in the sweet area for efficiency to about 125W it seems from this graph.

 

[nicalandia]

How likely will Intel be producing Sierra Forrest on Quad Tiles(as in SRP/EMR) than on a Huge Monolithic die?

This is how I envision Sierra Forrest(perhaps not as complex as SPR-S)


I believe the e core clusters are perfect for cloud computing since most of those are either virtualized single, dual or quad core instances/containers

 

[BorisTheBlade82]

How likely will Intel be producing Sierra Forrest on Quad Tiles(as in SRP/EMR) than on a Huge Monolithic die?

This is how I envision Sierra Forrest(perhaps not as complex as SPR-S)
View attachment 70614

I believe the e core clusters are perfect for cloud computing since most of those are either virtualized single, dual or quad core instances/containers

AFAIR they will switch to a topology like AMD with Sierra Forest - IOD + Core-Dies.

 

[nicalandia]

AFAIR they will switch to a topology like AMD with Sierra Forest - IOD + Core-Dies.

That is by far the Least likelihood of all possible outcomes(like 100 and that would be the 100th)

 

[igor_kavinski]

I see no problem with Meteor Lake having a further improved process and better memory controller performance.

It will take extra cycles for data to go from I/O die to compute die. It will need to be damn efficient to improve on Raptor Lake's RAM latency. They could cheat by using something like DDR5-6400 at CL28 as the stock setting.

 

[coercitiv]

Strange little reversal of E/P frequencies at 40W. I'm going to investigate that area further.

Yup, more or less the same behavior I saw on ADL:

The only time I've seen the power management go haywire was when I limited power bellow 35W: at that point something snapped in the internal logic, and IIRC I had to manually limit P core fmax to "help" power management make the correct choices again.

 

[Hulk]

Yup, more or less the same behavior I saw on ADL:

@coercitiv,
The reason I did this was because of your post regarding my trying to outsmart the Intel engineers at various power levels for E and P frequencies. I was curious.

 

[Exist50]

Even if we pretend that only INT matters I expect the lower ST peak performance will make E cores less competitive and more comparable to massive multi-core ARM chips and systems. But we will see, first Bergamo has to launch and then we will see how much urgency Intel feels to launch an "extremely competitive" E cores based chip in Sierra Forest.

If PPA were the sole priority ARM would dominate servers since years. Instead in the last couple of years it turned out that even on servers many workloads are limited by ST performance, and it's there that there has been some surprising demand for higher frequency server parts. As such if Sierra Forest is significantly below the ST peak performance of Xeon P core chips I don't expect it to see much use.

I think both Bergamo and Sierra Forest are in direct response to those massive multi-core ARM chips, so that comparison should be fine. As for ST peak, that space should be mostly covered by Turin and Granite Rapids (in 2024). Bergamo and Sierra Forest exist for throughput.

But on that note, I'm not so convinced Bergamo will pull much ahead in ST. We still don't know what exactly the frequency penalty will be for Zen 4c, and Intel's been scaling Atom's performance up rather aggressively. Also, as @BorisTheBlade82 points out, SMT is a major factor. If they enable it, then on a per thread basis, they will almost certainly be weaker than Atom, but if they don't enable it, then throughput tanks. Bit of a bind.

Bergamo on the other hand I expect to strike a balance that's more interesting to much of the server audience: higher efficiency and higher PPA, but same feature set and in all-cores loads likely peak frequencies pretty close to full fat server Zen 4 cores. I agree SMT is not of any significant importance here though.

I highly doubt Zen 4c will have similar frequencies to normal Zen 4. We know they're not lowering IPC, and it's the same process, so really the only knob left to get a lot of density/power gains is frequency reduction. If Zen 4c could hit clocks similar to Zen 4, then frankly Genoa wouldn't have much reason to exist at all.

 

[Exist50]

How likely will Intel be producing Sierra Forrest on Quad Tiles(as in SRP/EMR) than on a Huge Monolithic die?

This is how I envision Sierra Forrest(perhaps not as complex as SPR-S)
View attachment 70614

I believe the e core clusters are perfect for cloud computing since most of those are either virtualized single, dual or quad core instances/containers

AFAIR they will switch to a topology like AMD with Sierra Forest - IOD + Core-Dies.

IIRC, Sierra Forest is a contemporary to Granite Rapids, so it should look more like this:

But assuming they keep the amount of compute silicon similar to SPR, then they could pretty easily fit 2-300 Atom cores. More, even, if the GNR core count rumors are true.

 

[Exist50]

Sorry, I ment no gains against AMD Zen cores(a few post earlier someone was pointing out about Intel needing to have better performance/area than AMD)

Zen3 is 4 mm^2 vs Golden Cove 7 mm^2
Zen4 is 3.84 mm^2 vs Raptor Cove 8 mm^2
Zen5 will be about 3.4 mm^2 vs Redwood Cove 5.33 mm^2


Their design appear to be Identical in principle(shared L2, clusters and internal Ring)

Oh, and that makes more sense. Where are you getting that Zen 5 number from, however? They'll get very little density gains from N4, and will presumably have a lot of performance features that will push the area back up. Decent odds it's a bigger core than Zen 4, I think.

 

[BorisTheBlade82]

That is by far the Least likelihood of all possible outcomes(like 100 and that would be the 100th)

IIRC, Sierra Forest is a contemporary to Granite Rapids, so it should look more like this:
View attachment 70629
But assuming they keep the amount of compute silicon similar to SPR, then they could pretty easily fit 2-300 Atom cores. More, even, if the GNR core count rumors are true.

This information is from ServeTheHome when they were on some Intel Investor conference.

Intel Sierra Forest the E-Core Xeon Intel Needs

We discuss the Intel Sierra Forest announcement at Intel Investor Meeting 2022. This is the high E-core count chip Intel needs

www.servethehome.com

Intel is taking a page from the AMD playbook and is moving to a new chip design with Granite Rapids. It is disaggregating its uncore with its I/O and that is a huge portion of this announcement. Intel is effectively moving to the I/O die approach that AMD switched to in 2019 with the AMD EPYC Rome.