Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Mahboi]

This all looks impressive, first time I've been impressed by Intel in awhile.
I'm guessing AVX 512 isn't on the menu for Skymont?

 

[DavidC1]

We can't expect skymont or any other monts for at least one or two more generations to have real world performance comparable to GLC.

You barely see anyone asking for 16 Gracemont based chips do you? That's because single thread performance is still king. People want 8 Golden Coves over 16 Gracemonts. So when Skymont comes out there will be a faster P core, Lion Cove, and then people want many Lion Cove cores, not Golden Coves. And on and on and on.

This all looks impressive, first time I've been impressed by Intel in awhile.
I'm guessing AVX 512 isn't on the menu for Skymont?

They(leakers) aren't expecting AVX10.2 even with the successor. It looks like the E core team does what they want, which IMO is a good thing.

 

[Wolverine2349]

I often edit way after I post, so go read again. The E cores are still behind in clocks.

Yeah makessense then so they will still perform worse. How far behind in clocks.

Though Golden Cove IPC if true should be good. I remember hearing that Skmont was going to be more like Tiger Lake or Cypress Cove IPC and not Golden Cove.

Though Gracemont has Skylake IPC but behind in clocks and is worse in latency sensitive workload themselves. Though if it was possible to disable all P cores on 12th to 14th Gen and use just Gracemont, would it perform like a 9700K or double core count in case of 13th and 14th Gen i9s which has Skylake like IPC? Or not really?

 

[DavidC1]

Yeah makessense then so they will still perform worse. How far behind in clocks.

Though Golden Cove IPC if true should be good. I remember hearing that Skmont was going to be more like Tiger Lake or Cypress Cove IPC and not Golden Cove.

Obviously that was a guess. I was betting on it being Golden Cove+ for Integer looking at the history(30% for new uarchs), and that the leaker said they were aiming for "ADL", or Golden Cove.

Though Gracemont has Skylake IPC but behind in clocks and is worse in latency sensitive workload themselves. Though if it was possible to disable all P cores on 12th to 14th Gen and use just Gracemont, would it perform like a 9700K or double core count in case of 13th and 14th Gen i9s which has Skylake like IPC? Or not really?

They can do it in theory, and that's basically what they are doing with Sierra Forest. But I don't think it'll sell well in client.

If they were to do it they'll need to change the config to a single core setup rather than a module, have three tier caches, and connected to a high speed interconnect.

Gracemont is better than Skylake in Integer but worse in FP as well.

 

[DavidC1]

The graph seems to be showing 45% gain in Integer and 75% in FP, if it's linear. If that's the case, that explains both the core size increase, because it beats the typical 30% gain.

*Sniff* Atom is growing.

Being straight up increase in FP units, the performance improvement will be uniform rather than maybe as with new AVX standards.

Also,
Clearwater Forest

 

[Wolverine2349]

Obviously that was a guess. I was betting on it being Golden Cove+ for Integer looking at the history(30% for new uarchs), and that the leaker said they were aiming for "ADL", or Golden Cove.

They can do it in theory, and that's basically what they are doing with Sierra Forest. But I don't think it'll sell well in client.

If they were to do it they'll need to change the config to a single core setup rather than a module, have three tier caches, and connected to a high speed interconnect.

Gracemont is better than Skylake in Integer but worse in FP as well.

So they could do only e-cores in theory. Is there any reason why on 12th to 14th Gen you cannot disable all P cores and run with only the Gracemont e-cores in the BIOS? Is there any technical limitation to it or is it artificial from Intel and mobo makers that require at least one P core active form BIOS settings to POST and boot PC to an OS.

 

[DavidC1]

One guy on twitter is saying 37% is the official number, looks like that's the Integer figure. So the leakers were exactly right that it's aiming at "ADL". I did not expect the FP improvements though. So it'll beat Golden Cove in both Int and FP by about 10-15%.

Golden Cove has 3x 256-bit FP units. In applications where only 128-bits are used, 4x 128-bit on Skymont is more capable than on Golden Cove, because the 256-bit on Golden Cove is only taken advantage for 256-bit instructions.

 

[Henry swagger]

One guy on twitter is saying 37% is the official number, looks like that's the Integer figure. So the leakers were exactly right that it's aiming at "ADL". I did not expect the FP improvements though. So it'll beat Golden Cove in both Int and FP by about 10-15%.

Golden Cove has 3x 256-bit FP units. In applications where only 128-bits are used, 4x 128-bit on Skymont is more capable than on Golden Cove, because the 256-bit on Golden Cove is only taken advantage for 256-bit instructions.

Damn kopite was write with skymont having adl ipc.. can't wait for beast lake

 

[Philste]

Damn kopite was write with skymont having adl ipc.. can't wait for beast lake

Raichu also said the same. Goal is ADL/Cortex X(1). Which both have similar IPC.

 

[SiliconFly]

...Though if it was possible to disable all P cores on 12th to 14th Gen and use just Gracemont, would it perform like a 9700K or double core count in case of 13th and 14th Gen i9s which has Skylake like IPC? Or not really?

I don't think it'll even be close in ST.

 

[Wolverine2349]

I don't think it'll even be close in ST.

What Gracemont like Skylake ST performance or Skymont being close to Golden Cove single threaded performance?

 

[eek2121]

I have to LOL @ Intel for making Lunar Lake on TSMC N3B/N6 when their own latest process is supposedly superior.

 

[Hulk]

I have a feeling that the ARL/Zen 5 thing isn't going to be decided based on who jumps further ahead but more by who avoids an embarrassing stumble.

 

[coercitiv]

What Gracemont like Skylake ST performance or Skymont being close to Golden Cove single threaded performance?

You asked about Gracemont vs. Skylake. It would not be close in ST perf and would likely lose in mixed workloads as well. Keep in mind Skylake would have frequency advantage, inter-core latency advantage, memory latency advantage. Most consumer workloads would prefer these attributes over maximized throughput at 16 threads.

Also, where did you pull the Skylake close to GC ST performance from? The discussion is about IPC equivalence, not performance.

 

[Wolverine2349]

You asked about Gracemont vs. Skylake. It would not be close in ST perf and would likely lose in mixed workloads as well. Keep in mind Skylake would have frequency advantage, inter-core latency advantage, memory latency advantage. Most consumer workloads would prefer these attributes over maximized throughput at 16 threads.

Also, where did you pull the Skylake close to GC ST performance from? The discussion is about IPC equivalence, not performance.

So Gracemont not close to Skylake performance.

Also was asking about supposed Skymont Arrow Lake e-cores compared to Golden Cove. Will those have the IPC and latency and core to core communication of Golden Cove? Or not even close?

 

[poke01]

I have to LOL @ Intel for making Lunar Lake on TSMC N3B/N6 when their own latest process is supposedly superior.

It’s only superior when it’s out in volume.

 

[DavidC1]

Raichu also said the same. Goal is ADL/Cortex X(1). Which both have similar IPC.

Alderlake is X2 level. If you look at Windows Alderlake results versus Android then it seems to be around X1.

 

[JasonLD]

I have to LOL @ Intel for making Lunar Lake on TSMC N3B/N6 when their own latest process is supposedly superior.

Intel sharing EUV capacity on 4,3, and upcoming 20A. Intel will need TSMC until they have enough EUV capacity to produce at the same volume as Intel 7.

 

[DavidC1]

So Gracemont not close to Skylake performance.

Also was asking about supposed Skymont Arrow Lake e-cores compared to Golden Cove. Will those have the IPC and latency and core to core communication of Golden Cove? Or not even close?

Remember, Gracemont is faster on Integer but quite a bit slower on FP. So even if everything else is equal, the core differences mean the average equivalence really turns out to be lot of fluctuations.

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Golden Cove compared to Gracemont:
Int: +23%
FP: +66%

So based on those numbers Gracemont is 10% faster on Integer but Skylake is 22% faster in FP. Based on the differences between Zen 4 and ADL, gaming workloads favor FP more than Int.

We don't know if it'll have the same level as Golden Cove, but historically we can assume client parts won't be. They likely will need to do lot of low level changes to make it equal, and if Lion Cove is faster, why do that on the lower cost core?

 

[Ghostsonplanets]

I have to LOL @ Intel for making Lunar Lake on TSMC N3B/N6 when their own latest process is supposedly superior.

When LNL started development and they had to make a node choice, there was 0 confidence and foresight if they would have a competitive node by the time LNL would launch. Hence why ARL and LNL use TSMC N3B extensively, as reported by Nikkei back in 2020.

Panther Lake will come in 2025 H2 and make usage of Intel 18A and Intel 3 extensively.

 

[Mahboi]

Interesting, so it's a calendar reason?
I thought the decision was due to LNL aiming for low power draw and so TSMC N3 was deemed better than Intel 3.

 

[Ghostsonplanets]

Interesting, so it's a calendar reason?
I thought the decision was due to LNL aiming for low power draw and so TSMC N3 was deemed better than Intel 3.

Intel 3 literally didn't existed when Bob Swan did the deal for TSMC N3 (the original node) allocation.

 

[Magio]

Interesting, so it's a calendar reason?
I thought the decision was due to LNL aiming for low power draw and so TSMC N3 was deemed better than Intel 3.

It's possible that that's also the case, but regardless they don't have the capacity on N3 (or 20A even if it was library complete) for a launch as big as LNL and ARL are supposed to be.

 

[Joe NYC]

Yields? Intel7 must be yielding insanely good the last years so MTL didn't help with yields.

Intel told investors that Intel's pre-EUV nodes are very expensive and also said transition to EUV nodes will bring cost savings.

So unless Intel is BSing in an investor call, it would imply that Intel 7 yields are not good.

 

[Ghostsonplanets]

Intel told investors that Intel's pre-EUV nodes are very expensive and also said transition to EUV nodes will bring cost savings.

So unless Intel is BSing in an investor call, it would imply that Intel 7 yields are not good.

Years ago Intel CFO said that Intel 10/7 would never make the ROI for them, but it was a necessary step to overcome into ever so smaller and advanced manufacturing processess. So I guess it's kinda of both ways: Intel 7 is complex and expensive, but products are depreciated and in high-volume. While Intel 4+ brings costs-savings, but the product using it is more expensive to be made due to 3D tiled design + packaging.