Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[nicalandia]

Curious. This may be Intel's attempt to counter the AMD X3D parts.

No, its more of a System Level Cache for CPU and GPU. While L4 is better than RAM, its slower than L3

 

[Tigerick]

To me, Intel 7 essential similar like 10nm, same density just bigger die size.

By the end of 2025, we will see how many nodes of CPU Intel can produce. Out of 4 nodes, I am betting two nodes

 

[eek2121]

No, its more of a System Level Cache for CPU and GPU. While L4 is better than RAM, its slower than L3

It is still going to help. It will depend on the size and hit rate, of course.

 

[Exist50]

So it seems, as I have argued before, the MTL base tile may indeed not be passive, which makes sense given it’s a Foveros based design. Its a huge piece of silicon; it would be a wasted opportunity if it’s just being used as an interposer..

An active base die would cost significantly more than a passive one. If Intel does offer such a product for MTL/ARL, it would likely be a premium SKU only.

 

[ashFTW]

An active base die would cost significantly more than a passive one. If Intel does offer such a product for MTL/ARL, it would likely be a premium SKU only.

Maybe. But putting SRAM on the base die with very repetitive structure, on a very mature 22FFL process will yield very high. FDI (Foveros Die Interconnect) absolutely requires active circuits. I would rather put (most, if not all of) these on the base die and not on all the top die, in line with the separation of concerns design principle. That way you have smaller top die, and you make use of the ample space available on the base die.

This system level cache may actually be an integral part of the MTL/ARL SOC design; premium SKUs of course are likely to have relatively larger caches.

Edit: Also take a look at this Intel slide from last Hot Chips. Does it say “passive base die” to you?

HC34 Intel Meteor Lake Foveros Die Interconnect FDI - ServeTheHome

HC34 Intel Meteor Lake Foveros Die Interconnect FDI

www.servethehome.com

 

[igor_kavinski]

By the end of 2025, we will see how many nodes of CPU Intel can produce. Out of 4 nodes, I am betting two nodes

Actually just one node. Intel 4 which they will tweak a bit and call Intel 3. So that's how they get two nodes. Beyond that, I'm not very optimistic.

 

[Exist50]

Edit: Also take a look at this Intel slide from last Hot Chips. Does it say “passive base die” to you?

That's a horizontal cross-section, not a vertical one. All of that logic is on the active/top dies. For MTL, at least, the base is passive.

 

[ashFTW]

That's a horizontal cross-section, not a vertical one. All of that logic is on the active/top dies. For MTL, at least, the base is passive.

Did you see it says micro bumps on the slide??

 

[Exist50]

Did you see it says micro bumps on the slide??

Yes, there are microbumps connecting each of those two active dies to each other through the base die. In that diagram, the only thing that represents the base die is the purple wires.

 

[ashFTW]

Yes, there are microbumps connecting each of those two active dies to each other through the base die. In that diagram, the only thing that represents the base die is the purple wires.

Ok, that could make sense. But that’s EMIB territory. Don’t need a massive base die for it, and have all the added complexity of passing power to the top die through the base die.

 

[Exist50]

Ok, that could make sense. But that’s EMIB territory. Don’t need a massive base die for it, and have all the added complexity of passing power to the top die through the base die.

EMIB has a larger bump pitch than Foveros. In theory, ODI could be a solution, but that doesn't seem to be happening for MTL.

 

[ashFTW]

EMIB has a larger bump pitch than Foveros. In theory, ODI could be a solution, but that doesn't seem to be happening for MTL.

ODI would make sense if there are different sized top die reusing the same base die, which architecturally makes sense and something I have suggested before. It may happen in the future reusing the same base die. In any case, power still needs to be passed though the base die for the regions where the top and bottom die overlap.

I also realize that EMIB wouldn’t work for communicating between non adjacent die.

The top die have half of the FDI “contract”, which could communicate with the base die containing some sort of die interconnect fabric, or simply directly connect with another die with the other half of the contract, as suggested by the “purple wires” in the diagram. So designs with varying complexity are possible, with top die reuse.

 

[Exist50]

ODI would make sense if there are different sized top die reusing the same base die, which architecturally makes sense and something I have suggested before. It may happen in the future reusing the same base die. In any case, power will still needs to pass though the base die for the regions where the top and bottom die overlap.

I also realize that EMIB wouldn’t work for communicating between non adjacent die.

The top die have half of the FDI “contract”, which could communicate with the base die containing some sort of die interconnect fabric, or simply directly connect with another die with the other half of the contract, as suggested by the “purple wires” in the diagram. So designs with varying complexity are possible, with top die reuse.

ODI has a more Foveros-like dump pitch, which would be the key advantage for a design like MTL. And while in theory, a single base die could allow for some interesting topologies, in MTL, dies only communicate with their adjacents.

 

[ashFTW]

ODI has a more Foveros-like dump pitch, which would be the key advantage for a design like MTL. And while in theory, a single base die could allow for some interesting topologies, in MTL, dies only communicate with their adjacents.

As I understand it, ODI is an extension of base Foveros (it’s called Foveros Omni for a reason) with a smaller bump pitch, due to it being a “3rd generation“ Foveros.

EMIB has a larger bump pitch than Foveros. In theory, ODI could be a solution, but that doesn't seem to be happening for MTL.

According to this article, 1st and 2nd Gen EMIB and Foveros have identical bump pitches of 55 and 45 micro meters respectively. So I’m back to questioning use of Foveros if all communication is between adjacent die only. Unless it’s future proofing for more complex future designs enabling top die reuse.

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Intel unveils the Foveros Omni and Foveros Direct packaging technologies; which will be leveraging multiple base dies and hybrid bonding

fuse.wikichip.org

 

[Exist50]

As I understand it, ODI is an extension of base Foveros (it’s called Foveros Omni for a reason) with a smaller bump pitch, due to it being a “3rd generation“ Foveros.


According to this article, 1st and 2nd Gen EMIB and Foveros have identical bump pitches of 55 and 45 micro meters respectively. So I’m back to questioning use of Foveros if all communication is between adjacent die only. Unless it’s future proofing for more complex future designs enabling top die reuse.

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

Intel unveils the Foveros Omni and Foveros Direct packaging technologies; which will be leveraging multiple base dies and hybrid bonding

fuse.wikichip.org

Meteor Lake Foveros has a 36 micron bump pitch (shows in the Intel diagram on that page). Lakefield was 50 micron. Think the authors just made a mistake/typo.

 

[ashFTW]

Meteor Lake Foveros has a 36 micron bump pitch (shows in the Intel diagram on that page). Lakefield was 50 micron. Think the authors just made a mistake/typo.

Ok. I’m rewatching the Hot Chips MTL presentation now ..

 

[DrMrLordX]

Actually just one node. Intel 4 which they will tweak a bit and call Intel 3. So that's how they get two nodes. Beyond that, I'm not very optimistic.

If they can really deliver on 20a then there's hope for them. It (and 18a) are relatively new to the roadmaps, so Gelsinger and the people he brought in may have an outsized impact upon their development. Intel 4 is looking kind of shaky right now. Don't expect too much from it.

 

[ashFTW]

Ok. I’m rewatching the Hot Chips MTL presentation now ..

Ok I do agree the base tile is likely passive in MTL. Here is one of the Intel slides from HC34. Note the “Modularity with active silicon for memory and logic” that leaves the door open for more complex active base tiles.

 

[Exist50]

If they can really deliver on 20a then there's hope for them. It (and 18a) are relatively new to the roadmaps, so Gelsinger and the people he brought in may have an outsized impact upon their development. Intel 4 is looking kind of shaky right now. Don't expect too much from it.

I think it's worth noting what the particular rumor is as well. The claim is that MTL will be limited volume in '23, right? Well Intel's already kind of hinted that it will start shipping in H2, so these two details seem to align.

It takes about a quarter minimum between Intel/AMD/etc shipping the ships to OEMs and those chips showing up in laptops on shelves, and those are the high priority designs. For large volumes before the holiday shopping season, you'd want to ship in Q2 to give time for slow cargo ship transport to/from Asia. Trying to compress the schedule significantly means paying for (expensive) air cargo, which naturally means only the flagship designs make the cut. So it would be perfectly possible for MTL to enter volume production in Q3 and get a trickle of devices on shelves for Black Friday, with the true volume only coming in '24.

 

[Exist50]

Ok I do agree the base tile is passive in MTL. Here is one of the Intel slides from HC34.

View attachment 71941

Oh, good find. I don't remember seeing that one before. And they even explicitly say it could be swapped with an active die.

 

[ashFTW]

Oh, good find. I don't remember seeing that one before. And they even explicitly say it could be swapped with an active die.

Yeah. I just finished adding that to my original post

 

[ashFTW]

Yeah. I just finished adding that to my original post

MTL is quite a nice design, at least on paper. I’m impressed!! Let’s see how it’s in real life.

 

[DrMrLordX]

I think it's worth noting what the particular rumor is as well. The claim is that MTL will be limited volume in '23, right? Well Intel's already kind of hinted that it will start shipping in H2, so these two details seem to align.

It takes about a quarter minimum between Intel/AMD/etc shipping the ships to OEMs and those chips showing up in laptops on shelves, and those are the high priority designs. For large volumes before the holiday shopping season, you'd want to ship in Q2 to give time for slow cargo ship transport to/from Asia. Trying to compress the schedule significantly means paying for (expensive) air cargo, which naturally means only the flagship designs make the cut. So it would be perfectly possible for MTL to enter volume production in Q3 and get a trickle of devices on shelves for Black Friday, with the true volume only coming in '24.

Sadly that all means that Intel whiffs on the back-to-school crowd. Maybe there isn't as much activity in that vein right now due to over-saturation of the market with product from 2020 and 2021, but it's still a thing.

 

[Exist50]

Sadly that all means that Intel whiffs on the back-to-school crowd. Maybe there isn't as much activity in that vein right now due to over-saturation of the market with product from 2020 and 2021, but it's still a thing.

Oh yeah, it's a big miss for them either way. A couple units on shelves would be more about marketing than real revenue. I think the last major purchase cycle other than back to school and black friday would be the corporate refresh cycle (usually spring, iirc?), but that's probably shot given "pre-recession" cost cutting.

 

[Joe NYC]

To me, Intel 7 essential similar like 10nm, same density just bigger die size.

By the end of 2025, we will see how many nodes of CPU Intel can produce. Out of 4 nodes, I am betting two nodes

That would be my guess too. Intel 4 and Intel 3 parts.