Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[tamz_msc]

For the MT comparison it's 4x Skymont in LNL vs 2x Crestmont LP in MTL.

Why do you insist that LPE cores in LNL is equivalent to LP Island cores in MTL?

There is absolutely no indication that they are functionally the same.

 

[poke01]

Skymont is what makes LNL and ARL interesting. I really want to see a deep dive of this core.

 

[Kepler_L2]

Why do you insist that LPE cores in LNL is equivalent to LP Island cores in MTL?

There is absolutely no indication that they are functionally the same.

Because they are? All the leaked diagrams showed them without access to the L3 cache and call the 4x SKT cluster "LP island".

 

[tamz_msc]

Because they are? All the leaked diagrams showed them without access to the L3 cache and call the 4x SKT cluster "LP island".

So what?

The low power cluster has access to its own 8 MB SLC.

 

[Kepler_L2]

So what?

The low power cluster has access to its own 8 MB SLC.

View attachment 100073

Yeah that's not an L3 cache.

 

[tamz_msc]

Yeah that's not an L3 cache.

So what? For low priority tasks you don't need a low-latency caching subsystem. So the SLC can be away from the cores, and maybe even clock differently to save power. But it is a "Last Level" cache nonetheless.

It is increasingly becoming clear that MT perf of Skymont is being compared with Crestmont at the same core counts.

 

[Kepler_L2]

So what? For low priority tasks you don't need a low-latency caching subsystem. So the SLC can be away from the cores, and maybe even clock differently to save power. But it is a "Last Level" cache nonetheless.

It is increasingly becoming clear that MT perf of Skymont is being compared with Crestmont at the same core counts.

How is the MT perf increase so much higher than ST perf increase? A puny 8MB System Level Cache is not going to result in 70% higher performance.

 

[Abwx]

So what? For low priority tasks you don't need a low-latency caching subsystem. So the SLC can be away from the cores, and maybe even clock differently to save power. But it is a "Last Level" cache nonetheless.

It is increasingly becoming clear that MT perf of Skymont is being compared with Crestmont at the same core counts.

It s just that you cant have at the same time 1.7x the ST perf at same power + the same ST perf at 0.3x the power all while having 2.9x the MT perf at same power + same MT perf at 0.3x the power with the same core count.

At same core count if you have 2.9x the MT perf at same power then it should be the same MT perf at about 0.12x the power since power scale as a square of performance.

If you take 1.7x ST perf at same power with one core then with 4 cores you ll get 6.8x the perf at 4x the power in MT, and hence 2.9x the MT perf at same power than 2C, this is assuming a square law, and that s in line with the single core being at 1.7x the perf at isowatt, so Kepler is right on this one.

 

[tamz_msc]

How is the MT perf increase so much higher than ST perf increase? A puny 8MB System Level Cache is not going to result in 70% higher performance.

Lower MT frequency penalty vs Crestmont due to differences between N3B and Intel 4 is one possibility.

The other one (and more likely) being that this isn't a comparison with Lunar Lake as the underlying SoC, but Arrow Lake.

In which case it will be an apples to apples comparison with both having access to LLC.

 

[Mahboi]

At some point, diminishing returns will hit the E core like they do for every design. These huge gains are the product of 1) starting with a lower baseline, and 2) giving way more transistor budget to the design than before. It used to be ~4 E-cores equal the area of 1 P-core, and with Skymont it's closer to 2:1. While I don't doubt they could probably scale up the E core's performance if they were given the P core's transistor budget, they won't get 2x the performance. If I recall correctly, a rule of thumb for ST performance is that it's roughly proportional to the square root of the transistor budget, so with 2x the transistors a core should have ~40% higher ST performance.

Obviously, but that doesn't change the P core situation does it?
It's now a steaming hot failure because it went past diminishing returns long ago.
Starting fresh with the Monts as the new growing baseline makes a lot more sense. Or would, if Zen 5 wasn't cornering Intel in a few days.

 

[AMDK11]

The thing has no chances against anything Zen5.

Am I wrong to sense doubt and fear in you?

 

[Joe NYC]

Am I wrong to sense doubt and fear in you?

Fear of a hypothetical 12P core Intel client CPU that is not on any roadmap?

 

[Mahboi]

We're meant to fear the unknown, not the non-existant.

 

[DavidC1]

The thing has no chances against anything Zen5.

Didn't you also say "no chance" when I said expecting 30% gains(which they beat here by a huge amount) with Skymont?

Those increases seem astronomical. I hope they aren't.

It's not.

For FP performance, scaling up the number of units benefits wider workloads because you don't need recompiling while using new ISA like AVX does. So in FP it's straight up faster that way.

In Integer, it is consistent with previous gains of 30%, but they seem to be scaling up this time.

By the way Lion Cove is supposed to have 4x 256-bit vector now so the gain will be uniform too.

 

[DavidC1]

IDC in absolute shambles. Almost guaranteed we get Conroe 2.0 in a few years.

The Austin Atom team has been far more innovative and willing to try new ideas than IDC ever was, even back during their peak.

Read back into Anandtech's article about Bonnell.

-Goldmont with pre-decode cache
-Tremont with clustered decode
-Skymont with the Nanocode

Atom team is beating the P core team like rabbit vs turtle comparison. Now the E core has scaled up a lot, each step the turtle takes is comparatively massive.

C&C posted an article on Skymont, which has some interesting technical discussion. Enjoy!

Thoughts on Skymont Slides

Recently a set of Skymont slides were published, apparently without any embargo or confidentiality marks. I have no proof that the slides are genuine. However, I think they’re worth analyzing…

chipsandcheese.com

-96 byte fetch(up from 64 byte in Gracemont and 32 in Golden Cove)

C&C is WRONG about it being 16 ports, when leakers said it was 20+ and Gracemont already has 17 ports.

My inference is that Keller made a far bigger impression with the Atom team than IDC.

He's just one man. Go look at the history again. They executed with consistency. That's what got them here. Previously they thought "useless" Atom cores so no one gave attention. Keller might have helped them but earlier posts say the 12-wide core(future Atom) is the beneficiary, not this one. Credit is all on the team, not Tech Jesus.

 

[Mahboi]

Noob question of the day: what is nanocode exactly?

 

[DavidC1]

If the 38%/68% gains are against Crestmont:
It'll be 18% faster than Golden Cove in Integer and 6% faster in FP.

It's near Cortex X4 level, not X2.

Noob question of the day: what is nanocode exactly?

We don't know.

 

[Mahboi]

We don't know.

I downgrade you to DavidD1.
(Hopefully Kepler knows and won't be downgraded into Kepler_L3)

More seriously, it would not be above Intel to compare vs Tremont or something of the sort. They were not above comparing Raptor Lake to Ice Lake for some benchmarks where the progress was too low.

 

[DavidC1]

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18% faster with 3x the core size difference. Saying the P core is in shambles is an understatement.

This is what I mean that the uop cache is doomed folks. I agree with Eric Quinnell on this.

 

[itsmydamnation]

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18% faster with 3x the core size difference. Saying the P core is in shambles is an understatement.

This is what I mean that the uop cache is doomed folks. I agree with Eric Quinnell on this.

Why? The other vendors core with a far larger uop cache has no such problems.

to quote my daughter , skill issue.

 

[tamz_msc]

I've said it many times before that Gracemont was already at Sunny Cove/Cypress Cove-level IPC, at least for integer.

I had no doubt in my mind that the initial claims where it was said that Skymont is targeting ADL level performance would be true in the end.

 

[tamz_msc]

18% faster with 3x the core size difference.

TBH most of the area comes from transistors aimed at sustaining 5.5 GHz or more fMax.

 

[DavidC1]

TBH most of the area comes from transistors aimed at sustaining 5.5 GHz or more fMax.

Not just for spacing but for things such as extra pipeline stages and uop caches(which are a remnant of the high clock speed era).

IMO even Atom should pair down on the clocks, and go from 14 stages to 10-12 stages.

 

[Philste]

Skymont gains just got confirmed from Computerbase Editor, also "double digit IPC gains" for Lion Cove.

 

[csbin]

Skymont gains just got confirmed from Computerbase Editor, also "double digit IPC gains" for Lion Cove.

Link?