Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[DavidC1]

Assuming Hyperthreading gives 1.3x benefit, and Lion Cove is 20% faster:

Raptorlake
-1x P core x 1.3 x 8
-1x E cores x 16
Total: 26.4

Arrowlake
-1.2x P core x 8
-1.4 x E cores x 16
Total: 32

21% advantage for Arrowlake assuming a well multi-threaded application. For the P cores it's 9.6 vs 10.4, so the losses aren't big. Likely, the faster single thread portion can make up for loss of multi-threaded performance in many applications that aren't perfectly threaded, and it'll be many.

It may also be more correct to assume a 1.5x modifier for Skymont because client workloads use quite a bit of FP it seems. The faster E core relative to the P core will further reduce cases where there are sudden performance drops, and the lack of HT will likely help too. It looks like games use a fair bit of SIMD code too, this is where the doubled vector units will be a boon.

Bionic_Squash also says Lion Cove goes to 4x256-bit SIMD. It's FP performance should improve significantly.

 

[Wolverine2349]

Skymont may well be a good architecture but being on tile might be what doesn't let it perform to its fullest.

Yes thats possibly true.

Just like for some reason Sapphire Rapids Golden Cove has gimped IPC compared to client Golden Cove due to mesh arch instead of ring bus.

It sucks because Xeon Workstation is not a good substitute for getting more than 8 P cores on Golden Cove or above unlike Broadwell E and prior. Not only is it more expensive requiring ECC RAM, the platform is so different and has too many enterprise features detrimental to things like gaming unlike HEDT Broadwell E and prior back in the day which were more like mainstream desktop on steroids rather than Enterprise workstation.

And HEDT was less expensive too. But even besides cost, Xeon SPR Workstation not a good option for gaming as it has gimped lPC and latency unlike Broadwell E and prior and ECC RAM required which is detrimental to things like gaming.

Xeon Workstation these days you are paying the premium for things like so many more PCIe lanes and ECC RAM and advanced platform. Better single thread performance its not unlike Boradwell E and before which were basically just quad channel RA and ore cores and a little more PCIe and still excellent gaming and single thread and multi thread performance.

 

[igor_kavinski]

Xeon Workstation these days you are paying the premium for things like so many more PCIe lanes and ECC RAM and advanced platform. Better single thread performance its not unlike Boradwell E and before which were basically just quad channel RA and ore cores and a little more PCIe and still excellent gaming and single thread and multi thread performance.

Yeah there are users on this forum who used Xeons for gaming and many even now may buy them used for gaming coz they are dirt cheap. I was certainly considering one to replace my 65W i7-5775C coz the Xeon eDRAM part is 95W so it would definitely perform a bit better.

 

[Wolverine2349]

Yeah there are users on this forum who used Xeons for gaming and many even now may buy them used for gaming coz they are dirt cheap. I was certainly considering one to replace my 65W i7-5775C coz the Xeon eDRAM part is 95W so it would definitely perform a bit better.

Yes some old ones cause they are so cheap but performant they are not unlike prior Intel HEDT.

Well older arch Xeons had more in common with their desktop counterparts than todays Xeons, but they are locked, but at least latency and IPC was not gimped in favor of all these glamourous more expensive enterprise features that gimp the IPC of modern Xeons where fewer faster cores for gaming than a bunch of slow lower IPC cores and also lower clocked. But still a little above 8 would be nice. You had those options and for less money too on X99 and before unlike today's Xeons for gaming.

 

[AMDK11]

Do you remember the news and reports from 2021?

Intel Post-Core 'Royal Core' Era Rumors: Lunar Lake To Bring 30% IPC Improvement Over Meteor Lake With Lion Cove Cores, Tackling AMD Zen 5 Core in 2024

Intel's Royal Core project for next-gen Arrow Lake, Lunar Lake & Nova Lake CPUs based on Lion Cove and Panther Cove architecture has leaked.

wccftech.com

 

[Kepler_L2]

Do you remember the news and reports from 2021?

Intel Post-Core 'Royal Core' Era Rumors: Lunar Lake To Bring 30% IPC Improvement Over Meteor Lake With Lion Cove Cores, Tackling AMD Zen 5 Core in 2024

Intel's Royal Core project for next-gen Arrow Lake, Lunar Lake & Nova Lake CPUs based on Lion Cove and Panther Cove architecture has leaked.

wccftech.com

Lunar Lake is not Royal Core, and MLID was talking about LNC not Skymont.

 

[AMDK11]

Lunar Lake is not Royal Core, and MLID was talking about LNC not Skymont.

And I'm talking about LionCove.

 

[Kepler_L2]

And I'm talking about LionCove.

Yeah that one is not 30% IPC. Just saying that you shouldn't quote MLID because he will try to retcon he was talking about 30%+ IPC gain for Skymont the whole time.

 

[Philste]

38% SpecINT 68% SpecFP "solid upgrade" according to MLID sauces

 

[inf64]

Assuming Hyperthreading gives 1.3x benefit, and Lion Cove is 20% faster:

Raptorlake
-1x P core x 1.3 x 8
-1x E cores x 16
Total: 26.4

Arrowlake
-1.2x P core x 8
-1.4 x E cores x 16
Total: 32

21% advantage for Arrowlake assuming a well multi-threaded application. For the P cores it's 9.6 vs 10.4, so the losses aren't big. Likely, the faster single thread portion can make up for loss of multi-threaded performance in many applications that aren't perfectly threaded, and it'll be many.

It may also be more correct to assume a 1.5x modifier for Skymont because client workloads use quite a bit of FP it seems. The faster E core relative to the P core will further reduce cases where there are sudden performance drops, and the lack of HT will likely help too. It looks like games use a fair bit of SIMD code too, this is where the doubled vector units will be a boon.

Bionic_Squash also says Lion Cove goes to 4x256-bit SIMD. It's FP performance should improve significantly.

One problem, Lion Cove and Raptor Cove P core sustained clockspeeds will likely be very different (read: Raptor cove will likely run at noticeably higher clock in any nT mode). So not only that Lion Cove P cores will have to deal with the lack of SMT, they will have to match 5.5Ghz all core turbo for your calculation to be close to reality.

 

[DavidC1]

One problem, Lion Cove and Raptor Cove P core sustained clockspeeds will likely be very different (read: Raptor cove will likely run at noticeably higher clock in any nT mode). So not only that Lion Cove P cores will have to deal with the lack of SMT, they will have to match 5.5Ghz all core turbo for your calculation to be close to reality.

It's true. Arrowlake and Lunarlake is a strange combination of two overlapping era cores together, as if you had Netburst and Core.

The MT gains will still be decent, because most is offered by the E cores. The P core would need to be less than half before you start losing performance.

The question is how much faster is Lion Cove over Skymont? 20% Int and 30-35% FP means only a clockspeed advantage in Int and 25% faster in FP.

 

[Hulk]

Like the results for SpecCPU shows, Golden Cove is 23%/66% faster in Int and FP respectively.

If you take 5% for Crestmont and add 38% for Int and 68% for FP, you get my figure.

Of course for real world applications it will vary, and Spec is also a composite benchmark so some tests will do better than others. I'm talking about overall. "Outright" of course depends on the context. If they are clocked the same it should be in the ballpark I said.

Think of Nehalem vs Penryn. Nehalem is basically Penryn with a vastly improved memory and communications system. Nearly the same core, but greatly enhanced uncore.

So as a core Skymont is very competent just like Gracemont was. Darkmont-based Clearwater Forest on 18A with Foveros Direct sounds good to me.

Okay these figures, not your post, are nuts!
If Skymont is on par with Golden Cove from an IPC point-of-view then the performance between Skymont and Lion Cove will amount to perhaps 20% IPC and frequency advantage for LC. If this pans out then ARL will be a beast both in terms of performance and economics for Intel.

 

[AMDK11]

Think of Nehalem vs Penryn. Nehalem is basically Penryn with a vastly improved memory and communications system. Nearly the same core, but greatly enhanced uncore.

I don't agree with that. Nehalem is a new core architecture that has been redesigned and expanded. The scale of changes and expansion may seem small nowadays, but it is certainly not nearly Penryn.

 

[AMDK11]

Fear of a hypothetical 12P core Intel client CPU that is not on any roadmap?

NO. Will Zen5 cope with the competition(LionCove)

 

[AMDK11]

Okay these figures, not your post, are nuts!
If Skymont is on par with Golden Cove from an IPC point-of-view then the performance between Skymont and Lion Cove will amount to perhaps 20% IPC and frequency advantage for LC. If this pans out then ARL will be a beast both in terms of performance and economics for Intel.

I believe Skymont is just an appetizer and LionCove is the main course. I find LionCove much faster than Skymont. Computex is just a few days away and I expect the LionCove slides to be released by weekend.

Very big changes do not only concern Skymont. There are huge changes taking place, especially at LionCove, as you will see for yourself.

The LunarLake graphic doesn't tell everything about LionCove, just like it doesn't tell everything about Skymont. Based on the Skymont diagram, I thought there were even fewer execution units than in Gracemont. Only the Intel slide leak shows huge changes.

The same will happen with LionCove.

If anyone has any doubts about this, they will find out for themselves within maybe not even days, but hours.

EDIT:
LionCove is not only about huge changes or reconstruction, but also Intel's new approach to architecture with the highest possible IPC. LionCove, among others, implements new techniques.

 

[Henry swagger]

I believe Skymont is just an appetizer and LionCove is the main course. I find LionCove much faster than Skymont. Computex is just a few days away and I expect the LionCove slides to be released by weekend.

Very big changes do not only concern Skymont. There are huge changes taking place, especially at LionCove, as you will see for yourself.

The LunarLake graphic doesn't tell everything about LionCove, just like it doesn't tell everything about Skymont. Based on the Skymont diagram, I thought there were even fewer execution units than in Gracemont. Only the Intel slide leak shows huge changes.

The same will happen with LionCove.

If anyone has any doubts about this, they will find out for themselves within maybe not even days, but hours.

EDIT:
LionCove is not only about huge changes or reconstruction, but also Intel's new approach to architecture with the highest possible IPC. LionCove, among others, implements new techniques.

interesting

 

[DavidC1]

I don't agree with that. Nehalem is a new core architecture that has been redesigned and expanded. The scale of changes and expansion may seem small nowadays, but it is certainly not nearly Penryn.

You can disagree but it's true. Nehalem's main focus is everything other than the core. Which was badly needed for sure.

When you isolate the uarch the gains are like a Tick. 5-10%. It's not wider in any way either nor brought any noticeable improvements.

 

[adroc_thurston]

I don't agree with that. Nehalem is a new core architecture that has been redesigned and expanded. The scale of changes and expansion may seem small nowadays, but it is certainly not nearly Penryn.

The core was pretty much Penryn with like 3.5 server-focused changes.
The new stuff was everything not core (new $ hierarchy, IMC, new not-Hypertransport etc).
Beckton (-EX) went even further and became the first Intel chip with a ringbus.

 

[DavidC1]

@Exist50 has said that the E core team was subject to being shuttered if they did not execute and also they adopted the new better approach of designing processors years ago.

The P core team has been wasting a lot of resources and time exactly because they were on top and became complacent. At this point it's more than complacency - it's delusion.

 

[adroc_thurston]

At this point it's more than complacency - it's delusion.

Yeah.
Fortunately, they're about to be removed out of existence.

 

[AMDK11]

You can disagree but it's true. Nehalem's main focus is everything other than the core. Which was badly needed for sure.

When you isolate the uarch the gains are like a Tick. 5-10%. It's not wider in any way either nor brought any noticeable improvements.

Following this line of reasoning, SandyBridge is almost a Nehalem core because it is not wider at all (the decoding is the same width and the number of execution units remains the same).

 

[AMDK11]

@Exist50 has said that the E core team was subject to being shuttered if they did not execute and also they adopted the new better approach of designing processors years ago.

The P core team has been wasting a lot of resources and time exactly because they were on top and became complacent. At this point it's more than complacency - it's delusion.

He also believed that LionCove belongs to "RoyalCore" and what does that mean?

 

[AMDK11]

You can disagree but it's true. Nehalem's main focus is everything other than the core. Which was badly needed for sure.

When you isolate the uarch the gains are like a Tick. 5-10%. It's not wider in any way either nor brought any noticeable improvements.

NO. The single core of Nehalem, apart from the width, i.e. the number of streams, does not resemble and is not close to Penryn.

 

[DavidC1]

Following this line of reasoning, SandyBridge is almost a Nehalem core because it is not wider at all (the decoding is the same width and the number of execution units remains the same).

Yes but Sandy Bridge brings innovative new ideas and actually improves performance significantly.

-Physical Register Files
-uOP Cache, which is a hugely improved Trace Cache
-Rebuilt branch predictor for efficiency taking up same space but with twice the targets
-Load/Store units that also improve efficiency
-256-bit vector by reusing ports, saving space
-Finally to top it off, a ring bus that allows high bandwidth communication and ultra low latency access for the L3 while allowing modularity in design
-Turbo 2.0 that is actually innovative taking advantage of thermal headroom for bursty applications rather than simple core count based as with Nehalem.

While Nehalem does improve performance though, it's mostly in memory bandwidth limited applications and high thread. Back when Xbitlabs was active they did a really good test comparing Nehalem versus Penryn at equal clocks with Turbo on/off and SMT on/off. It showed that in real single threaded applications it was a glorified Tick with 5-10% gain and the rest were based on much needed changes unrelated to the core such as the integrated memory controller.

The guys at RWT did a test too and noted that with Nehalem there are even circumstances where performance degrades with single thread. It was everything BUT single thread.

The two teams complemented each other very well with one enhancing the core(IDC) and the other enhancing the uncore(Oregon).

 

[AMDK11]

Yes but Sandy Bridge brings innovative new ideas and actually improves performance significantly.

-Physical Register Files
-uOP Cache, which is a hugely improved Trace Cache
-Rebuilt branch predictor for efficiency taking up same space but with twice the targets
-Load/Store units that also improve efficiency
-256-bit vector by reusing ports, saving space
-Finally to top it off, a ring bus that allows high bandwidth communication and ultra low latency access for the L3 while allowing modularity in design
-Turbo 2.0 that is actually innovative taking advantage of thermal headroom for bursty applications rather than simple core count based as with Nehalem.

While Nehalem does improve performance though, it's mostly in memory bandwidth limited applications and high thread. Back when Xbitlabs was active they did a really good test comparing Nehalem versus Penryn at equal clocks with Turbo on/off and SMT on/off. It showed that in real single threaded applications it was a glorified Tick with 5-10% gain and the rest were based on much needed changes unrelated to the core such as the integrated memory controller.

The guys at RWT did a test too and noted that with Nehalem there are even circumstances where performance degrades with single thread. It was everything BUT single thread.

The two teams complemented each other very well with one enhancing the core(IDC) and the other enhancing the uncore(Oregon).

I never wrote that Nehalem (x86 core) is a breakthrough. I wrote that it's definitely not Conroe/Peneyn. SMT implementation, all architecture modes (Marco and micro) have been adapted for x64, which was not available in Conreoe/Penryn. Even some functions have been moved before the decoding stage and to extended buffers, a new predictor, etc. Writing that Nehalem is roughly Penryn is an oversimplification.

The IPC drop in some cases was caused by changing the cache subsystem from very large L2 to very small L2 and large unified L3.

Edit:

Features a 33% wider instruction window and overall new control logic. All this and changes throughout the system have made Nehalem a big generational leap.